Chris Wilkerson
Affiliations:- Intel
According to our database1,
Chris Wilkerson
authored at least 51 papers
between 1996 and 2023.
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Bibliography
2023
CoRR, 2023
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023
2018
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018
Proceedings of the 15th ACM International Conference on Computing Frontiers, 2018
2017
A Case for Memory Content-Based Detection and Mitigation of Data-Dependent Failures in DRAM.
IEEE Comput. Archit. Lett., 2017
Detecting and mitigating data-dependent DRAM failures by exploiting current memory content.
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017
Kill the Program Counter: Reconstructing Program Behavior in the Processor Cache Hierarchy.
Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems, 2017
2016
Reducing Performance Impact of DRAM Refresh by Parallelizing Refreshes with Accesses.
CoRR, 2016
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016
2015
Proceedings of the 48th International Symposium on Microarchitecture, 2015
2014
The efficacy of error mitigation techniques for DRAM retention failures: a comparative experimental study.
Proceedings of the ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems, 2014
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014
Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors.
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014
Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014
Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014
Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014
2013
An experimental study of data retention behavior in modern DRAM devices: implications for retention time profiling mechanisms.
Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013
2012
MorphCore: An Energy-Efficient Microarchitecture for High Performance ILP and High Throughput TLP.
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012
2011
IEEE Trans. Computers, 2011
IEEE J. Solid State Circuits, 2011
Error Detection and Correction in Microprocessor Core and Memory Due to Fast Dynamic Voltage Droops.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011
Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011
2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010
Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
2009
Impact of Die-to-Die and Within-Die Parameter Variations on the Clock Frequency and Throughput of Multi-Core Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2009
Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance.
IEEE J. Solid State Circuits, 2009
Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009
Proceedings of the 46th Design Automation Conference, 2009
2008
Energy-Efficient and Metastability-Immune Timing-Error Detection and Instruction-Replay-Based Recovery Circuits for Dynamic-Variation Tolerance.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
Proceedings of the 35th International Symposium on Computer Architecture (ISCA 2008), 2008
2007
Proceedings of the SPAA 2007: Proceedings of the 19th Annual ACM Symposium on Parallelism in Algorithms and Architectures, 2007
Impact of die-to-die and within-die parameter variations on the throughput distribution of multi-core processors.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007
2006
Proceedings of the SPAA 2006: Proceedings of the 18th Annual ACM Symposium on Parallelism in Algorithms and Architectures, Cambridge, Massachusetts, USA, July 30, 2006
2005
2003
IEEE Micro, 2003
Improving Branch Prediction by Dynamic Dataflow-Based Identification of Correlated Branches from a Large Global History.
Proceedings of the 30th International Symposium on Computer Architecture (ISCA 2003), 2003
Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-Order Processors.
Proceedings of the Ninth International Symposium on High-Performance Computer Architecture (HPCA'03), 2003
2002
Proceedings of the 35th Annual International Symposium on Microarchitecture, 2002
2001
Proceedings of the 28th Annual International Symposium on Computer Architecture, 2001
1998
Proceedings of the 25th Annual International Symposium on Computer Architecture, 1998
1996
Proceedings of the ASPLOS-VII Proceedings, 1996