Yoongu Kim

According to our database¹, Yoongu Kim authored at least 28 papers between 2004 and 2022.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of three.

Timeline

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PhD thesis

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On csauthors.net:

Bibliography

2022

Half-Double: Hammering From the Next Row Over.

[BibT_eX]

[DOI]

Proceedings of the 31st USENIX Security Symposium, 2022

2018

Predictable Performance and Fairness Through Accurate Slowdown Estimation in Shared Main Memory Systems.

[BibT_eX]

[DOI]

CoRR, 2018

RowClone: Accelerating Data Movement and Initialization Using DRAM.

[BibT_eX]

[DOI]

Rachata Ausavarungnirun

CoRR, 2018

Tiered-Latency DRAM: Enabling Low-Latency Main Memory at Low Cost.

[BibT_eX]

[DOI]

CoRR, 2018

Adaptive-Latency DRAM: Reducing DRAM Latency by Exploiting Timing Margins.

[BibT_eX]

[DOI]

CoRR, 2018

Exploiting the DRAM Microarchitecture to Increase Memory-Level Parallelism.

[BibT_eX]

[DOI]

CoRR, 2018

Reducing DRAM Refresh Overheads with Refresh-Access Parallelism.

[BibT_eX]

[DOI]

CoRR, 2018

2017

Improving DRAM Performance by Parallelizing Refreshes with Accesses.

[BibT_eX]

[DOI]

CoRR, 2017

2016

Tiered-Latency DRAM (TL-DRAM).

[BibT_eX]

[DOI]

CoRR, 2016

Adaptive-Latency DRAM (AL-DRAM).

[BibT_eX]

[DOI]

CoRR, 2016

RowHammer: Reliability Analysis and Security Implications.

[BibT_eX]

[DOI]

CoRR, 2016

Reducing Performance Impact of DRAM Refresh by Parallelizing Refreshes with Accesses.

[BibT_eX]

[DOI]

CoRR, 2016

Ramulator: A Fast and Extensible DRAM Simulator.

[BibT_eX]

[DOI]

Yoongu Kim

Weikun Yang

Onur Mutlu

IEEE Comput. Archit. Lett., 2016

2015

Adaptive-latency DRAM: Optimizing DRAM timing for the common-case.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

2014

The efficacy of error mitigation techniques for DRAM retention failures: a comparative experimental study.

[BibT_eX]

[DOI]

Proceedings of the ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems, 2014

Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors.

[BibT_eX]

[DOI]

Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014

Improving DRAM performance by parallelizing refreshes with accesses.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

Memory Systems.

[BibT_eX]

Yoongu Kim

Onur Mutlu

Proceedings of the Computing Handbook, 2014

2013

RowClone: fast and energy-efficient in-DRAM bulk data copy and initialization.

[BibT_eX]

[DOI]

Rachata Ausavarungnirun

Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013

Linearly compressed pages: a low-complexity, low-latency main memory compression framework.

[BibT_eX]

[DOI]

Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013

An experimental study of data retention behavior in modern DRAM devices: implications for retention time profiling mechanisms.

[BibT_eX]

[DOI]

Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

MISE: Providing performance predictability and improving fairness in shared main memory systems.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013

Tiered-latency DRAM: A low latency and low cost DRAM architecture.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013

2012

A case for exploiting subarray-level parallelism (SALP) in DRAM.

[BibT_eX]

[DOI]

Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012

2011

Thread Cluster Memory Scheduling.

[BibT_eX]

[DOI]

IEEE Micro, 2011

2010

Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior.

[BibT_eX]

[DOI]

Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010

ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers.

[BibT_eX]

[DOI]

Proceedings of the 16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), 2010

2004

S-COI : The Secure Conflicts of Interest Model for Multilevel Secure Database Systems.

[BibT_eX]

[DOI]

Chanjung Park

Seog Park

Yoongu Kim

Proceedings of the Database Systems for Advances Applications, 2004

Yoongu Kim

Timeline

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