Kyo Yun Lee
According to our database1,
Kyo Yun Lee
authored at least 4 papers
between 2018 and 2024.
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Bibliography
2024
13.4 A 48GB 16-High 1280GB/s HBM3E DRAM with All-Around Power TSV and a 6-Phase RDQS Scheme for TSV Area Optimization.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
A 192-Gb 12-High 896-GB/s HBM3 DRAM With a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization.
IEEE J. Solid State Circuits, 2023
2022
A 192-Gb 12-High 896-GB/s HBM3 DRAM with a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2018
A 1.2V 64Gb 341GB/S HBM2 stacked DRAM with spiral point-to-point TSV structure and improved bank group data control.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018