Kyungjun Cho
Orcid: 0000-0003-4589-8099
According to our database1,
Kyungjun Cho
authored at least 8 papers
between 2015 and 2024.
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Bibliography
2024
13.4 A 48GB 16-High 1280GB/s HBM3E DRAM with All-Around Power TSV and a 6-Phase RDQS Scheme for TSV Area Optimization.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
A 192-Gb 12-High 896-GB/s HBM3 DRAM With a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization.
IEEE J. Solid State Circuits, 2023
2022
A 192-Gb 12-High 896-GB/s HBM3 DRAM with a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2019
Low Leakage Electromagnetic Field Level and High Efficiency Using a Novel Hybrid Loop-Array Design for Wireless High Power Transfer System.
IEEE Trans. Ind. Electron., 2019
2018
Microelectron. J., 2018
2016
Design and analysis of on-interposer active power distribution network for an efficient simultaneous switching noise suppression in 2.5D IC.
Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016
2015
Electrical performance of high bandwidth memory (HBM) interposer channel in terabyte/s bandwidth graphics module.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015
Crosstalk-included eye-diagram estimation for high-speed silicon, organic, and glass interposer channels on 2.5D/3D IC.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015