Yuhua Liang

Orcid: 0000-0003-1240-2878

According to our database1, Yuhua Liang authored at least 32 papers between 2012 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2024
A 102.1-dB SNDR oversampling merge-mismatch-error-shaping SAR ADC in 180 nm CMOS.
Microelectron. J., January, 2024

A 93.4-dB SNDR single-ended SAR ADC with a hybrid R-C DAC.
Microelectron. J., January, 2024

Analysis of non-ideal factors for a high precision interpolated resistor string DAC.
Microelectron. J., January, 2024

2023
A Time-Domain Reconfigurable Second-Order Noise Shaping ADC With Single Fan-Out Gated Delay Cells.
IEEE Trans. Very Large Scale Integr. Syst., June, 2023

A Reconfigurable 12-to-18-Bit Dynamic Zoom ADC With Pole-Optimized Technique.
IEEE Trans. Circuits Syst. I Regul. Pap., May, 2023

A configurable area-efficient LCoS chip design with centrosymmetric pixel array.
Microelectron. J., 2023

A 99.93% energy-efficient switching scheme for SAR ADC without switching energy in the first three MSBs.
Microelectron. J., 2023

LMS-based digital background mismatch calibration technique for SAR ADC.
Microelectron. J., 2023

A reconfigurable 8-to-12-b 10-MS/s energy-efficient two-step ADC.
Microelectron. J., 2023

An energy-efficient switching scheme based on a splitting structure.
Microelectron. J., 2023

2022
A 625kHz-BW, 79.3dB-SNDR Second-Order Noise-Shaping SAR ADC Using High-Efficiency Error-Feedback Structure.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

A Power-Efficient TVC-Based Fast Auto-Frequency Calibration for PLLs.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

A 14-b 20-MS/s 78.8 dB-SNDR Energy-Efficient SAR ADC With Background Mismatch Calibration and Noise-Reduction Techniques for Portable Medical Ultrasound Systems.
IEEE Trans. Biomed. Circuits Syst., 2022

Radio frequency analog-to-digital converters: Systems and circuits review.
Microelectron. J., 2022

2021
A 5 MHz-BW 71.7-dB SNDR two-step hybrid-domain ADC in 65-nm CMOS.
Microelectron. J., 2021

A statistical offset calibration technique for 1.5-bit/cycle SAR ADCs.
Microelectron. J., 2021

2020
Enhanced CEST MRI Using the Residual of Inversed Z-Spectra for Ischemia Detection.
IEEE Access, 2020

2019
Utilization of Negative-Capacitance FETs to Boost Analog Circuit Performances.
IEEE Trans. Very Large Scale Integr. Syst., 2019

A 10-Bit 5 MS/s VCO-SAR ADC in 0.18-µm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

2018
A 10bit 20 kS/s 17.7 nW 9.1ENOB reference-insensitive SAR ADC in 0.18 μm CMOS.
Microelectron. J., 2018

A 42ppm/∘C 0.7V 47nW Low-Complexity All-MOSFET Sub-Threshold Voltage Reference.
J. Circuits Syst. Comput., 2018

Analysis and Modeling of a SAR-VCO Hybrid ADC Architecture.
J. Circuits Syst. Comput., 2018

An Energy-Efficient Switching Scheme for Low-Power SAR ADC Design.
J. Circuits Syst. Comput., 2018

2017
A 0.6 V 31 nW 25 ppm/°C MOSFET-only sub-threshold voltage reference.
Microelectron. J., 2017

2015
A 0.6-V 38-nW 9.4-ENOB 20-kS/s SAR ADC in 0.18- μm CMOS for Medical Implant Devices.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

A 10-bit 300-MS/s asynchronous SAR ADC with strategy of optimizing settling time for capacitive DAC in 65 nm CMOS.
Microelectron. J., 2015

Calibration algorithm for 16-bit voltage-mode R-2R DAC.
Microelectron. J., 2015

A Gain-Tunable Output Buffer for Audio-DAC with Common-Mode Output Independent of Gain Variation.
J. Circuits Syst. Comput., 2015

Strategy for SAR ADC with 87.5% area saving and 99.4% switching energy reduction over conventional approach.
IEICE Electron. Express, 2015

Ultra-low energy switching scheme for SAR ADC.
IEICE Electron. Express, 2015

2012
Synchronization of Non-Identical Unknown Chaotic Delayed Neural Networks Based on Adaptive Sliding Mode Control.
Neural Process. Lett., 2012

Synchronization of chaotic neural networks with time delay in the leakage term and parametric uncertainties based on sampled-data control.
J. Frankl. Inst., 2012


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