Luigi Dadda

M. Pisoni

Marco D. Santambrogio

Proceedings of the 15th IEEE International Conference on Computational Science and Engineering, 2012

2008

A variant of a radix-10 combinational multiplier.

[BibT_eX]

[DOI]

Alberto Nannarelli

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007

Multioperand Parallel Decimal Adder: A Mixed Binary and BCD Approach.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2007

A Memory Unit for Priority Management in IPSec Accelerators.

[BibT_eX]

[DOI]

Alberto Ferrante

Proceedings of IEEE International Conference on Communications, 2007

2005

Quasi-Pipelined Hash Circuits.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE Symposium on Computer Arithmetic (ARITH-17 2005), 2005

2004

An ASIC design for a high speed implementation of the hash function SHA-256 (384, 512).

[BibT_eX]

[DOI]

Jeff Owen

Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

The Design of a High Speed ASIC Unit for the Hash Function SHA-256 (384, 512).

[BibT_eX]

[DOI]

Jeff Owen

Proceedings of the 2004 Design, 2004

1998

A VLSI inner product macrocell.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1998

1997

Fast Arithmetic and Fault Tolerance in the FERMI System.

[BibT_eX]

[DOI]

Proceedings of the 1997 International Conference on Application-Specific Systems, 1997

1996

Pipelined Adders.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1996

1995

Bit-modular defect/fault-tolerant convolvers.

[BibT_eX]

[DOI]

Proceedings of the 1995 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1995

Column Compression Pipelined Multipliers.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Application Specific Array Processors (ASAP'95), 1995

1994

Fault-Tolerant Modular Convolves.

[BibT_eX]

Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1994

A processor for calorimetry at the Large Hadron Collider in the FERMI project.

[BibT_eX]

[DOI]

Sami J. Inkinen

Proceedings of the International Conference on Application Specific Array Processors, 1994

1993

A Simplified High Speed Parallel Input Convolver.

[BibT_eX]

[DOI]

Proceedings of the Sixth International Conference on VLSI Design, 1993

System Level Policies for Fault Tolerance Issues in the FERMI Project.

[BibT_eX]

Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993

Multi-parallel convolvers.

[BibT_eX]

[DOI]

Renato Stefanelli

Proceedings of the 11th Symposium on Computer Arithmetic, 29 June, 1993

1990

A polyphase architecture for serial-input convolvers.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 1990

Testing of serial input convolvers.

[BibT_eX]

[DOI]

Donatella Sciuto

Microprocessing and Microprogramming, 1990

Byte-serial convolvers.

[BibT_eX]

[DOI]

Proceedings of the Application Specific Array Processors, 1990

1989

On Serial-Input Multipliers for Two's Complement Numbers.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1989

Polyphase convolvers.

[BibT_eX]

[DOI]

Proceedings of the 9th Symposium on Computer Arithmetic, 1989

1988

A serial-input serial-output bit-sliced convolver.

[BibT_eX]

[DOI]

Proceedings of the Computer Design: VLSI in Computers and Processors, 1988

1985

Squarers for binary numbers in serial form.

[BibT_eX]

[DOI]

Proceedings of the 7th IEEE Symposium on Computer Arithmetic, 1985

Fast multipliers for two's-complement numbers in serial form.

[BibT_eX]

[DOI]

Proceedings of the 7th IEEE Symposium on Computer Arithmetic, 1985

1983

Some schemes for fast serial input multipliers.

[BibT_eX]

[DOI]

Proceedings of the 6th IEEE Symposium on Computer Arithmetic, 1983

1980

Composite Parallel Counters.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1980

1978

Multiple addition of binary serial numbers.

[BibT_eX]

[DOI]