Luigi Dadda
According to our database^{1},
Luigi Dadda
authored at least 25 papers
between 1978 and 2012.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2000, "For contributions in the field of arithmetic architectures for computers and DSP systems.".
Timeline
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Bibliography
2012
A ParallelSerial Decimal Multiplier Architecture.
Proceedings of the 15th IEEE International Conference on Computational Science and Engineering, 2012
2008
A variant of a radix10 combinational multiplier.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
2007
Multioperand Parallel Decimal Adder: A Mixed Binary and BCD Approach.
IEEE Trans. Computers, 2007
A Memory Unit for Priority Management in IPSec Accelerators.
Proceedings of IEEE International Conference on Communications, 2007
2005
QuasiPipelined Hash Circuits.
Proceedings of the 17th IEEE Symposium on Computer Arithmetic (ARITH17 2005), 2005
2004
An ASIC design for a high speed implementation of the hash function SHA256 (384, 512).
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004
The Design of a High Speed ASIC Unit for the Hash Function SHA256 (384, 512).
Proceedings of the 2004 Design, 2004
1998
A VLSI inner product macrocell.
IEEE Trans. VLSI Syst., 1998
1997
Fast Arithmetic and Fault Tolerance in the FERMI System.
Proceedings of the 1997 International Conference on ApplicationSpecific Systems, 1997
1996
Pipelined Adders.
IEEE Trans. Computers, 1996
1995
Bitmodular defect/faulttolerant convolvers.
Proceedings of the 1995 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1995
Column Compression Pipelined Multipliers.
Proceedings of the International Conference on Application Specific Array Processors (ASAP'95), 1995
1994
FaultTolerant Modular Convolves.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1994
A processor for calorimetry at the Large Hadron Collider in the FERMI project.
Proceedings of the International Conference on Application Specific Array Processors, 1994
1993
A Simplified High Speed Parallel Input Convolver.
Proceedings of the Sixth International Conference on VLSI Design, 1993
System Level Policies for Fault Tolerance Issues in the FERMI Project.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993
Multiparallel convolvers.
Proceedings of the 11th Symposium on Computer Arithmetic, 29 June, 1993
1990
A polyphase architecture for serialinput convolvers.
VLSI Signal Processing, 1990
1989
On SerialInput Multipliers for Two's Complement Numbers.
IEEE Trans. Computers, 1989
Polyphase convolvers.
Proceedings of the 9th Symposium on Computer Arithmetic, 1989
1985
Squarers for binary numbers in serial form.
Proceedings of the 7th IEEE Symposium on Computer Arithmetic, 1985
Fast multipliers for two'scomplement numbers in serial form.
Proceedings of the 7th IEEE Symposium on Computer Arithmetic, 1985
1983
Some schemes for fast serial input multipliers.
Proceedings of the 6th IEEE Symposium on Computer Arithmetic, 1983
1980
Composite Parallel Counters.
IEEE Trans. Computers, 1980
1978
Multiple addition of binary serial numbers.
Proceedings of the 4th IEEE Symposium on Computer Arithmetic, 1978