Fabio Salice

According to our database1, Fabio Salice authored at least 93 papers between 1993 and 2019.

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Bibliography

2019
Wellness Indexes to Assess Quality of Life: a technological support.
Proceedings of the 5th EAI International Conference on Smart Objects and Technologies for Social Good, 2019

Understanding Home Inactivity for Human Behavior Anomaly Detection.
Proceedings of the 5th EAI International Conference on Smart Objects and Technologies for Social Good, 2019

2018
CC4CS: an Off-the-Shelf Unifying Statement-Level Performance Metric for HW/SW Technologies.
Proceedings of the Companion of the 2018 ACM/SPEC International Conference on Performance Engineering, 2018

Supporting Alzheimer's Residential Care - A Novel Indoor Localization System.
Proceedings of the 15th International Joint Conference on e-Business and Telecommunications, 2018

Non-invasive monitoring system to detect sitting people.
Proceedings of the 4th EAI International Conference on Smart Objects and Technologies for Social Good, 2018

2017
ALMA: An Indoor Localization and Navigation System for the Elderly.
Proceedings of the Smart Objects and Technologies for Social Good, 2017

Quantitative Indicators for Behaviour Drift Detection from Home Automation Data.
Proceedings of the Harnessing the Power of Technology to Improve Lives, 2017

Human Behavior Drift Detection in a Smart Home Environment.
Proceedings of the Harnessing the Power of Technology to Improve Lives, 2017

2016
Indoor Activity Monitoring for Mutual Reassurance.
Proceedings of the Smart Objects and Technologies for Social Good, 2016

PIR Probability Model for a Cost/Reliability Tradeoff Unobtrusive Indoor Monitoring System.
Proceedings of the Smart Objects and Technologies for Social Good, 2016

Maps for Easy Paths (MEP): Enriching Maps with Accessible Paths Using MEP Traces.
Proceedings of the Smart Objects and Technologies for Social Good, 2016

2015
Method, Design and Implementation of an Indoor Tracking System with Concurrent Fault Localization.
EAI Endorsed Trans. Ubiquitous Environments, 2015

An Expert CAD Flow for Incremental Functional Diagnosis of Complex Electronic Boards.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

Bridge: Mutual Reassurance for Autonomous and Independent Living.
IEEE Intelligent Systems, 2015

SHARON: a Simulator of Human Activities, ROutines and Needs.
Proceedings of the Assistive Technology, 2015

BRIDGeViz: Towards an Interactive Data Visualization Tool for Exploration of Indoor Daily Life of an Older Adult.
Proceedings of the Assistive Technology, 2015

ODINS: On-Demand Indoor Navigation System RFID Based.
Proceedings of the Assistive Technology, 2015

2014
Towards a Hand-Based Gestural Language for Smart-Home Control Using Hand Shapes and Dynamic Hand Movements.
Proceedings of the Ubiquitous Computing and Ambient Intelligence. Personalisation and User Adapted Services, 2014

Method, design and implementation of a multiuser indoor localization system with concurrent fault detection.
Proceedings of the 11th International Conference on Mobile and Ubiquitous Systems: Computing, 2014

Method, Design and Implementation of a Self-checking Indoor Localization System.
Proceedings of the Ambient Assisted Living and Daily Activities, 2014

Personalized Hand Pose and Gesture Recognition System for the Elderly.
Proceedings of the Universal Access in Human-Computer Interaction. Aging and Assistive Environments, 2014

Static hand poses for gestural interaction: a study.
Proceedings of the International Working Conference on Advanced Visual Interfaces, 2014

2013
A data mining approach to incremental adaptive functional diagnosis.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

2011
Optimal Test Set Selection for Fault Diagnosis Improvement.
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

2010
Improving fault diagnosis accuracy by automatic test set modification.
Proceedings of the 2011 IEEE International Test Conference, 2010

A Formal Condition to Stop an Incremental Automatic Functional Diagnosis.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

Test Selection Policies for Faster Incremental Fault Detection.
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

2009
An Incremental Approach to Functional Diagnosis.
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

2008
Software and Hardware Techniques for SEU Detection in IP Processors.
J. Electronic Testing, 2008

Convolutional Coding for SEU mitigation.
Proceedings of the 13th European Test Symposium, 2008

A Generalized Approach for the Use of Convolutional Coding in SEU Mitigation.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

A performance-oriented hardware/software partitioning for datapath applications.
Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, 2008

2007
Exploring Partial Reconfiguration for Mitigating SEU faults in SRAM-Based FPGAs.
Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2007

A New Framework for Design and Simulation of Complex Hardware/Software Systems.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

RAM-Based Fault Tolerant State Machines for FPGAs.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

2006
Affinity-Driven System Design Exploration for Heterogeneous Multiprocessor SoC.
IEEE Trans. Computers, 2006

Evolving classifiers on field programmable gate arrays: Migrating XCS to FPGAs.
Journal of Systems Architecture, 2006

2005
A model of soft error effects in generic IP processors.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

Reliable System Specification for Self-Checking Data-Paths.
Proceedings of the 2005 Design, 2005

Toward an FPGA implementation of XCS.
Proceedings of the IEEE Congress on Evolutionary Computation, 2005

2004
Discrete-Event Modeling and Simulation of Superscalar Microprocessor Architectures.
Proceedings of the Integrated Circuit and System Design, 2004

Reliable System Co-Design: The FIR Case Study.
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

Analysis and Modeling of Energy Reducing Source Code Transformations.
Proceedings of the 2004 Design, 2004

An area estimation methodology for FPGA based designs at systemc-level.
Proceedings of the 41th Design Automation Conference, 2004

Source-Level Models for Software Power Optimization.
Proceedings of the Ultra Low-Power Electronics and Design, 2004

2003
Logical and physical design issues for smart card databases.
ACM Trans. Inf. Syst., 2003

The design of reliable devices for mission-critical applications.
IEEE Trans. Instrumentation and Measurement, 2003

Partitioning of Embedded Applications onto Heterogeneous Multiprocessor Architectures.
Proceedings of the 2003 ACM Symposium on Applied Computing (SAC), 2003

An Internal Representation Model for System-Level Co-Design of Heterogeneous Multiprocessor Embedded System.
Proceedings of the Forum on specification and Design Languages, 2003

An Integrated Design Approach for Self-Checking FPGAs.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

A First Step Towards Hw/Sw Partitioning of UML Specifications.
Proceedings of the 2003 Design, 2003

Library Functions Timing Characterization for Source-Level Analysis.
Proceedings of the 2003 Design, 2003

Early estimation of the size of VHDL projects.
Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003

2002
Static power modeling of 32-bit microprocessors.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

The Impact of Source Code Transformations on Software Power and Energy Consumption.
Journal of Circuits, Systems, and Computers, 2002

Physical and Logical Data Structures for Very Small Databases.
Proceedings of the Decimo Convegno Nazionale su Sistemi Evoluti per Basi di Dati, 2002

Modeling Assembly Instruction Timing in Superscalar Architectures.
Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

A System Level Approach in Designing Dual-Duplex Fault Tolerant Embedded Systems.
Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002

Fault-Tolerant CAM Architectures: A Design Framework.
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

Designing Self-Checking FPGAs through Error Detection Codes.
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

Metrics for design space exploration of heterogeneous multiprocessor embedded systems.
Proceedings of the Tenth International Symposium on Hardware/Software Codesign, 2002

2001
On-line fault detection in a hardware/software co-design environment.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Dynamic modeling of inter-instruction effects for execution time estimation.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Designing Reliable Embedded Systems Based on 32 Bit Microprocessors.
Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001

Reliability Properties Assessment at System Level: A Co-design Framework.
Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001

An Assembly-Level Execution-Time Model for Pipelined Architectures.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

A Software Methodology for Detecting Hardware Faults in VLIW Data Paths.
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

Development cost and size estimation starting from high-level specifications.
Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001

Source-level execution time estimation of C programs.
Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001

2000
Design of VHDL-based totally self-checking finite-state machine and data-path descriptions.
IEEE Trans. VLSI Syst., 2000

A Case Study in Design Space Exploration: The Tosca Environment Applied to a Telecommunication Link Controller.
IEEE Design & Test of Computers, 2000

A Multi-Level Strategy for Software Power Estimation.
Proceedings of the 13th International Symposium on System Synthesis, 2000

An instruction-level functionally-based energy estimation model for 32-bits microprocessors.
Proceedings of the 37th Conference on Design Automation, 2000

Energy estimation for 32-bit microprocessors.
Proceedings of the Eighth International Workshop on Hardware/Software Codesign, 2000

1999
A Synthesis Methodology Aimed at Improving the Quality of TSC Devices.
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999

1998
Fault Analysis for Networks with Concurrent Error Detection.
IEEE Design & Test of Computers, 1998

Concurrent Error Detection at Architectural Level.
Proceedings of the 11th International Symposium on System Synthesis, 1998

System-level performance estimation strategy for sw and hw.
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

Fault Analysis in Networks with Concurrent Error Detection Properties.
Proceedings of the 1998 Design, 1998

A Model for System-Level Timed Analysis and Profiling.
Proceedings of the 1998 Design, 1998

1997
A TSC Evaluation Function for Combinational Circuits.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

Improving Design Turnaround Time via Two-Levels Hw/Sw Co-Simulation.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

Parity Bit Code: Achieving a Complete Fault Coverage in the Design of TSC Combinational Networks.
Proceedings of the 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 1997

Designing Networks with Error Detection Properties through the Fault-Error Relation.
Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997

A novel methodology for designing TSC networks based on the parity bit code.
Proceedings of the European Design and Test Conference, 1997

A Flexible Model for Evaluating the Behavior of Hardware/Software Systems.
Proceedings of the Fifth International Workshop on Hardware/Software Codesign, 1997

1996
Redundant Faults in TSC Networks: Definition and Removal.
Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996

1995
A new architecture for the automatic design of custom digital neural network.
IEEE Trans. VLSI Syst., 1995

Behavior of Self-Checking Checkers for 1-out-of-3 Codes Based on Pass-Transistor Logic.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

A BDD Based Algorithm for Detecting Difficult Faults.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Self-checking FSMs based on a constant distance state encoding.
Proceedings of the 1995 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1995

1994
Synthesis of Multi-level Self-Checking Logic.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1994

1993


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