Marco Macchetti

According to our database1, Marco Macchetti authored at least 20 papers between 2002 and 2016.

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Bibliography

2016
Evaluating physically unclonable functions on a large set of FPGAs.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

Evaluating the Impact of Environmental Factors on Physically Unclonable Functions (Abstract Only).
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

2013
Cryptanalysis of AES and Camellia with Related S-boxes.
Proceedings of the Progress in Cryptology, 2013

2009
Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology.
Trans. Comput. Sci., 2009

Revisiting the IDEA Philosophy.
Proceedings of the Fast Software Encryption, 16th International Workshop, 2009

2007
Area and Power Efficient Synthesis of DPA-Resistant Cryptographic S-Boxes.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies.
Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, 2007

A Memory Unit for Priority Management in IPSec Accelerators.
Proceedings of IEEE International Conference on Communications, 2007

2006
ASIC hardware implementation of the IDEA NXT encryption algorithm.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
Characteristics of Key-Dependent S-Boxes: the Case of Twofish.
IACR Cryptol. ePrint Arch., 2005

A Complete Formulation of Generalized Affine Equivalence.
Proceedings of the Theoretical Computer Science, 9th Italian Conference, 2005

Quasi-Pipelined Hash Circuits.
Proceedings of the 17th IEEE Symposium on Computer Arithmetic (ARITH-17 2005), 2005

2004
Addendum to "On the Generalized Linear Equivalence of Functions over Finite Fields".
IACR Cryptol. ePrint Arch., 2004

Efficient AES implementations for ARM based platforms.
Proceedings of the 2004 ACM Symposium on Applied Computing (SAC), 2004

An ASIC design for a high speed implementation of the hash function SHA-256 (384, 512).
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

Power-efficient ASIC synthesis of cryptographic sboxes.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

The Design of a High Speed ASIC Unit for the Hash Function SHA-256 (384, 512).
Proceedings of the 2004 Design, 2004

On the Generalized Linear Equivalence of Functions Over Finite Fields.
Proceedings of the Advances in Cryptology, 2004

2003
About the performances of the Advanced Encryption Standard in embedded systems with cache memory.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002
Efficient Software Implementation of AES on 32-Bit Platforms.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2002


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