Mariagiovanna Sami

According to our database1, Mariagiovanna Sami authored at least 76 papers between 1973 and 2014.

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Bibliography

2014
Fault-Tolerant Network Interfaces for Networks-on-Chip.
IEEE Trans. Dependable Sec. Comput., 2014

Embedded Systems Education: Job Market Expectations.
Proceedings of the Workshop on Embedded and Cyber-Physical Systems Education, 2014

Virtual semi-concurrent self-checking for heterogeneous MPSoC architectures.
Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014

2013
An OpenCL-based feature matcher.
Sig. Proc.: Image Comm., 2013

A system-level approach to adaptivity and fault-tolerance in NoC-based MPSoCs: The MADNESS project.
Microprocessors and Microsystems - Embedded Hardware Design, 2013

MRI parallel processing for embedded visualization.
Proceedings of the IEEE Third International Conference on Consumer Electronics, 2013

2012
Optimal Design of Wireless Sensor Networks.
Proceedings of the Methodologies and Technologies for Networked Enterprises, 2012

System Adaptivity and Fault-Tolerance in NoC-based MPSoCs: The MADNESS Project Approach.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

2011
ADSC: Application-Driven Storage Control for Energy Efficiency.
Proceedings of the Information and Communication on Technology for the Fight against Global Warming, 2011

Design of Fault Tolerant Network Interfaces for NoCs.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

Analyzing the Sensitivity to Faults of Synchronization Primitives.
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

2009
Guest Editor's introduction.
Journal of Systems Architecture - Embedded Systems Design, 2009

2008
Modelling the power cost of security in Wireless Sensor Networks : The case of 802.15.4.
Proceedings of the 2008 International Conference on Telecommunications, 2008

Code Generation from Statecharts: Simulation of Wireless Sensor Networks.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

2007
Self-adaptive Security at Application Level: a Proposal.
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007

StateCharts to systemc: a high level hardware simulation approach.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Security Aspects in Networks-on-Chips: Overview and Proposals for Secure Implementations.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

2005
Low-power branch prediction techniques for VLIW architectures: a compiler-hints based approach.
Integration, 2005

Reducing the complexity of instruction-level power models for VLIW processors.
Design Autom. for Emb. Sys., 2005

Flexible Power Modeling for Wireless Systems: Power Modeling and Optimization of two Bluetooth Implementations.
Proceedings of the 2005 International Conference on a World of Wireless, 2005

Multithreaded Extension to Multicluster VLIW Processors for Embedded Applications.
Proceedings of the 2005 Design, 2005

Energy/Performance Evaluation of the Multithreaded Extension of a Multicluster VLIW Processor.
Proceedings of the Seventh International Workshop on Computer Architectures for Machine Perception (CAMP 2005), 2005

2004
FSM--based power modeling of wireless protocols: the case of bluetooth.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

Power-aware branch prediction techniques: a compiler-hints based approach for VLIW processors.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

Embedded systems education: how to teach the required skills?
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004

2003
A Methodology for the Efficient Architectural Exploration of Energy-Delay Trade-offs for Embedded Systems.
Proceedings of the 2003 ACM Symposium on Applied Computing (SAC), 2003

Branch prediction techniques for low-power VLIW processors.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

2002
Low-power data forwarding for VLIW embedded architectures.
IEEE Trans. VLSI Syst., 2002

An instruction-level energy model for embedded VLIW architectures.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

SIMD Extension to VLIW Multicluster Processors for Embedded Applications.
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

Fault-Tolerant CAM Architectures: A Design Framework.
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

On-line Diagnosis and Reconfiguration of FPGA Systems.
Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

An Instruction-Level Methodology for Power Estimation and Optimization of Embedded VLIW Cores.
Proceedings of the 2002 Design, 2002

Energy estimation and optimization of embedded VLIW processors based on instruction clustering.
Proceedings of the 39th Design Automation Conference, 2002

2001
Semiconcurrent Error Detection in Data Paths.
IEEE Trans. Computers, 2001

Determining the Optimum Extended Instruction-Set Architecture for Application Specific Reconfigurable VLIW CPUs.
Proceedings of the 12th IEEE International Workshop on Rapid System Prototyping (RSP 2001), 2001

Exploiting data forwarding to reduce the power budget of VLIW embedded processors.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000
Guest Editors' Introduction.
IEEE Trans. Computers, 2000

Power Exploration for Embedded VLIW Architectures.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Determining the optimum extended instruction-set architecture for application specific reconfigurable VLIW CPUs (poster abstract).
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2000

Instruction-level power estimation for embedded VLIW cores.
Proceedings of the Eighth International Workshop on Hardware/Software Codesign, 2000

1999
A DAG-Based Design Approach for Reconfigurable VLIW Processors.
Proceedings of the 1999 Design, 1999

1998
Testability analysis and behavioral testing of the Hopfield neural paradigm.
IEEE Trans. VLSI Syst., 1998

Co-Testing: Granting Testability in a Codesign Environment.
Integrated Computer-Aided Engineering, 1998

Minimizing the Application Time for Manufacturer Testing of FPGA (Abstract).
Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, 1998

Designing for Yield: A Defect-Tolerant Approach to High-Level Synthesis.
Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998

High-level Synthesis of Data Paths with Concurrent Error Detection.
Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998

A Low-Redundancy Approach to Semi-Concurrent Error Detection in Data Paths.
Proceedings of the 1998 Design, 1998

1997
A high-level synthesis approach to design of fault-tolerant systems.
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

Use of Statecharts-Related Description to Achieve Testable Design of Control Subsystems.
Proceedings of the 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 1997

Array partitioning to achieve defect tolerance.
Proceedings of the 23rd EUROMICRO Conference '97, 1997

Configuration-Specific Test Pattern Extraction for Field Programmable Gate Arrays.
Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997

Harvesting Through Array Partitioning: A Solution to Achieve Defect Tolerance.
Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997

Semi-Concurrent Error Detection in Data Paths.
Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997

1996
A high-level synthesis approach to optimum design of self-checking circuits.
Proceedings of the conference on European design automation, 1996

Context Reorder Buffer: An Architectural Support for Real-Time Processing on RISC Architectures.
Proceedings of the Eighth Euromicro Workshop on Real-Time Systems, 1996

KITE: a behavioural approach to fault-tolerance in FPGA-based systems.
Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996

Optimizing High-Level Synthesis for Self-Checking Arithmetic Circuits.
Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996

1995
Letter from the editors-in-chief.
Microprocessing and Microprogramming, 1995

Testability of artificial neural networks: A behavioral approach.
J. Electronic Testing, 1995

A Channel-Constrained Reconfiguration Approach for Processing Arrays.
Proceedings of the 1995 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1995

1994
Sensitivity to Errors in Artificial Neural Networks: a Behavioural Approach.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Synthesis of Multi-level Self-Checking Logic.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1994

1993
Concurrently self-checking structures for Fsms.
Microprocessing and Microprogramming, 1993


1992
Fault tolerance in FFT arrays: Time redundancy approaches.
VLSI Signal Processing, 1992

A behavioral approach to testability analysis for neural networks.
Microprocessing and Microprogramming, 1992

1991
Testing and diagnosis ofFFT arrays.
VLSI Signal Processing, 1991

1989
Reconfiguration of VLSI arrays by covering.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1989

Fault-tolerance through reconfiguration of VLSI and WSI awards.
MIT Press series in computer systems, MIT Press, ISBN: 978-0-262-14044-7, 1989

1986
Fault Tolerance Fechniques for Array Structures Used in Supercomputing.
IEEE Computer, 1986

Fault-Tolerance in Parallel Architectures.
Proceedings of the Future Parallel Computers, 1986

1983
Some Properties Derived from Structural Analysis of Program Graph Models.
IEEE Trans. Software Eng., 1983

Reconfigurable architectures for VLSI processing arrays.
Proceedings of the American Federation of Information Processing Societies: 1983 National Computer Conference, 1983

1982
Software testing techniques for universal building blocks of multimicrosystems.
Proceedings of the American Federation of Information Processing Societies: 1982 National Computer Conference, 1982

1973
Compression algorithms that preserve basic topological features in binary-coded patterns.
Pattern Recognition, 1973


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