Luca Breveglieri

According to our database1, Luca Breveglieri authored at least 79 papers between 1991 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of two.

Timeline

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Bibliography

2018
Fast deterministic parsers for transition networks.
Acta Inf., 2018

2016
A Fault-Based Secret Key Retrieval Method for ECDSA: Analysis and Countermeasure.
JETC, 2016

2015
BSP: A Parsing Tool for Ambiguous Regular Expressions.
Proceedings of the Implementation and Application of Automata, 2015

From Ambiguous Regular Expressions to Deterministic Parsing Automata.
Proceedings of the Implementation and Application of Automata, 2015

2014
Shift-Reduce Parsers for Transition Networks.
Proceedings of the Language and Automata Theory and Applications, 2014

Complexity of Extended vs. Classic LR Parsers.
Proceedings of the Descriptional Complexity of Formal Systems, 2014

2013
Formal Languages and Compilation, Second Edition.
Texts in Computer Science, Springer, ISBN: 978-1-4471-5514-0, 2013

A fault induction technique based on voltage underfeeding with application to attacks against AES and RSA.
Journal of Systems and Software, 2013

Parsing methods streamlined.
CoRR, 2013

2012
Interaction Between Fault Attack Countermeasures and the Resistance Against Power Analysis Attacks.
Proceedings of the Fault Analysis in Cryptography, 2012

Injection Technologies for Fault Attacks on Microprocessors.
Proceedings of the Fault Analysis in Cryptography, 2012

Fault Injection Attacks on Cryptographic Devices: Theory, Practice, and Countermeasures.
Proceedings of the IEEE, 2012

2011
Fault attack to the elliptic curve digital signature algorithm with multiple bit faults.
Proceedings of the 4th International Conference on Security of Information and Networks, 2011

2010
Efficient recognition of trace languages defined by repeat-until loops.
Inf. Comput., 2010

Low Voltage Fault Attacks to AES and RSA on General Purpose Processors.
IACR Cryptology ePrint Archive, 2010

Low Voltage Fault Attacks to AES.
Proceedings of the HOST 2010, 2010

Countermeasures against fault attacks on software implemented AES: effectiveness and cost.
Proceedings of the 5th Workshop on Embedded Systems Security, 2010

Fault attack on AES with single-bit induced faults.
Proceedings of the Sixth International Conference on Information Assurance and Security, 2010

2009
Alphabetical Satisfiability Problem for Trace Equations.
Acta Cybern., 2009

Practical Power Analysis Attacks to RSA on a Large IP Portfolio SoC.
Proceedings of the Sixth International Conference on Information Technology: New Generations, 2009

2008
A pairing SW implementation for Smart-Cards.
Journal of Systems and Software, 2008

Parallel Hardware Architectures for the Cryptographic Tate Pairing.
I. J. Network Security, 2008

A 640 Mbit/S 32-Bit Pipelined Implementation of the AES Algorithm.
Proceedings of the SECRYPT 2008, 2008

A FPGA Coprocessor for the Cryptographic Tate Pairing over Fp.
Proceedings of the Fifth International Conference on Information Technology: New Generations (ITNG 2008), 2008

Can Knowledge Regarding the Presence of Countermeasures Against Fault Attacks Simplify Power Attacks on Cryptographic Devices?.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

NP-completeness of the alphabetical satisfiability problem for trace equations.
Proceedings of the Automata and Formal Languages, 12th International Conference, 2008

2007
An Operation-Centered Approach to Fault Detection in Symmetric Cryptography Ciphers.
IEEE Trans. Computers, 2007

Programming Highly Parallel Reconfigurable Architectures for Symmetric and Asymmetric Cryptographic Applications.
JCP, 2007

Programming Highly Parallel Reconfigurable Architectures for Public-Key Cryptographic Applications.
Proceedings of the Fourth International Conference on Information Technology: New Generations (ITNG 2007), 2007

Countermeasures against Branch Target Buffer Attacks.
Proceedings of the Fourth International Workshop on Fault Diagnosis and Tolerance in Cryptography, 2007

Power Attacks Resistance of Cryptographic S-Boxes with Added Error Detection Circuits.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

2006
Guest Editors' Introduction: Special Section on Fault Diagnosis and Tolerance in Cryptography.
IEEE Trans. Computers, 2006

Power Aware Design of an Elliptic Curve Coprocessor for 8 bit Platforms.
Proceedings of the 4th IEEE Conference on Pervasive Computing and Communications Workshops (PerCom 2006 Workshops), 2006

ECC Hardware Coprocessors for 8-bit Systems and Power Consumption Considerations.
Proceedings of the Third International Conference on Information Technology: New Generations (ITNG 2006), 2006

Parallel Hardware Architectures for the Cryptographic Tate Pairing.
Proceedings of the Third International Conference on Information Technology: New Generations (ITNG 2006), 2006

A Note on Error Detection in an RSA Architecture by Means of Residue Codes.
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

Performance of HECC Coprocessors Using Inversion-Free Formulae.
Proceedings of the Computational Science and Its Applications, 2006

Incorporating Error Detection in an RSA Architecture.
Proceedings of the Fault Diagnosis and Tolerance in Cryptography, 2006

A Fault Attack Against the FOX Cipher Family.
Proceedings of the Fault Diagnosis and Tolerance in Cryptography, 2006

Software implementation of Tate pairing over GF(2m).
Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006

Speeding Up AES By Extending a 32 bit Processor Instruction Set.
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006

2005
A Parallelized Design for an Elliptic Curve Cryptosystem Coprocessor.
Proceedings of the International Symposium on Information Technology: Coding and Computing (ITCC 2005), 2005

AES Power Attack Based on Induced Cache Miss and Countermeasure.
Proceedings of the International Symposium on Information Technology: Coding and Computing (ITCC 2005), 2005

On-Line Testing for Secure Implementations: Design and Validation.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

A Complete Formulation of Generalized Affine Equivalence.
Proceedings of the Theoretical Computer Science, 9th Italian Conference, 2005

Incorporating Error Detection and Online Reconfiguration into a Regular Architecture for the Advanced Encryption Standard.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

2004
Finding Optimum Parallel Coprocessor Design for Genus 2 Hyperelliptic Curve Cryptosystems.
IACR Cryptology ePrint Archive, 2004

Efficient AES implementations for ARM based platforms.
Proceedings of the 2004 ACM Symposium on Applied Computing (SAC), 2004

Finding Optimum Parallel Coprocessor Design for Genus 2 Hyperelliptic Curve Cryptosystems.
Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'04), 2004

Workshop on Fault Diagnosis and Tolerance in Cryptography.
Proceedings of the 2004 International Conference on Dependable Systems and Networks (DSN 2004), 28 June, 2004

An Efficient Hardware-Based Fault Diagnosis Scheme for AES: Performances and Cost.
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

On the Generalized Linear Equivalence of Functions Over Finite Fields.
Proceedings of the Advances in Cryptology, 2004

Detecting Faults in Four Symmetric Key Block Ciphers.
Proceedings of the 15th IEEE International Conference on Application-Specific Systems, 2004

2003
Error Analysis and Detection Procedures for a Hardware Implementation of the Advanced Encryption Standard.
IEEE Trans. Computers, 2003

About the performances of the Advanced Encryption Standard in embedded systems with cache memory.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Detecting and Locating Faults in VLSI Implementations of the Advanced Encryption Standard.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

Concurrent Fault Detection in a Hardware Implementation of the RC5 Encryption Algorithm.
Proceedings of the 14th IEEE International Conference on Application-Specific Systems, 2003

2002
Digital Median Filters.
VLSI Signal Processing, 2002

A Parity Code Based Fault Detection for an Implementation of the Advanced Encryption Standard.
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

Efficient Software Implementation of AES on 32-Bit Platforms.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2002

On the Propagation of Faults and Their Detection in a Hardware Implementation of the Advanced Encryption Standard.
Proceedings of the 13th IEEE International Conference on Application-Specific Systems, 2002

2001
Efficient finite field digital-serial multiplier architecture for cryptography applications.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000
Dedicated Circuits for the Generation of Windows in Image Processing Architectures.
VLSI Signal Processing, 2000

1999
Modeling Operating Systems Schedulers with Multi-Stack-Queue Grammars.
Proceedings of the Fundamentals of Computation Theory, 12th International Symposium, 1999

1998
A VLSI inner product macrocell.
IEEE Trans. VLSI Syst., 1998

1997
Fair Expressions and Regular Languages over Lists.
ITA, 1997

Fast Arithmetic and Fault Tolerance in the FERMI System.
Proceedings of the 1997 International Conference on Application-Specific Systems, 1997

1996
Multi-Push-Down Languages and Grammars.
Int. J. Found. Comput. Sci., 1996

Balancing of Fault Tolerance in the New Version of the FERMI Channel Chip: a Functional Evaluation.
Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996

1995
Deterministic Parsing for Augmented Context-free Grammars.
Proceedings of the Mathematical Foundations of Computer Science 1995, 1995

A model for the evaluation of fault tolerance in the FERMI system.
Proceedings of the 1995 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1995

Column Compression Pipelined Multipliers.
Proceedings of the International Conference on Application Specific Array Processors (ASAP'95), 1995

1994
A fast pipelined FFT unit.
Proceedings of the International Conference on Application Specific Array Processors, 1994

1993
Modular design methodologies for image processing architectures.
IEEE Trans. VLSI Syst., 1993

Modular Design Methodologies for Image Processing Architectures.
Proceedings of the Sixth International Conference on VLSI Design, 1993

Fair First Languages and Parallel Programme Schemes.
Proceedings of the Developments in Language Theory, 1993


1992
Real-Time Scheduling by Queue Automata.
Proceedings of the Formal Techniques in Real-Time and Fault-Tolerant Systems, 1992

1991
Deterministic Dequeue Automata and LL(1) Parsing of Breadth-Depth Grammars.
Proceedings of the Fundamentals of Computation Theory, 8th International Symposium, 1991


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