Marc Erett

Orcid: 0000-0002-7681-1008

According to our database1, Marc Erett authored at least 7 papers between 2014 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
A 2.25pJ/bit Multi-lane Transceiver for Short Reach Intra-package and Inter-package Communication in 16nm FinFET.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018
A 112GB/S PAM4 Wireline Receiver Using a 64-Way Time-Interleaved SAR ADC in 16NM FinFET.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

A 126mW 56Gb/s NRZ wireline transceiver for synchronous short-reach applications in 16nm FinFET.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2017
A 0.5-16.3 Gbps Multi-Standard Serial Transceiver With 219 mW/Channel in 16-nm FinFET.
IEEE J. Solid State Circuits, 2017

2016
A 0.5-16.3Gbps multi-standard serial transceiver with 219mW/channel in 16nm FinFET.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

2015
A 0.5-16.3 Gb/s Fully Adaptive Flexible-Reach Transceiver for FPGA in 20 nm CMOS.
IEEE J. Solid State Circuits, 2015

2014
Wideband flexible-reach techniques for a 0.5-16.3Gb/s fully-adaptive transceiver in 20nm CMOS.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014


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