Chi Fung Poon

According to our database, Chi Fung Poon authored at least 6 papers between 2012 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

A 1.24-pJ/b 112-Gb/s (870 Gb/s/Mm) Transceiver for In-Package Links in 7-nm FinFET.

Chi Fung Poon, Wenfeng Zhang, Junho Cho, Shaojun Ma, Yipeng Wang, Ying Cao, Asma Laraba, Eugene Ho, Winson Lin, Zhaoyin Daniel Wu, Kee Hian Tan, Parag Upadhyaya, Yohan Frans

IEEE J. Solid State Circuits, 2022

2021

A 1.24pJ/b 112Gb/s (870Gbps/mm) Transceiver for In-package Links in 7nm FinFET.

Chi Fung Poon, Wenfeng Zhang, Junho Cho, Shaojun Ma, Yipeng Wang, Ying Cao, Asma Laraba, Eugene Ho, Winson Lin, Zhaoyin Daniel Wu, Kee Hian Tan, Parag Upadhyaya, Yohan Frans

Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

2019

A Fully Adaptive 19-58-Gb/s PAM-4 and 9.5-29-Gb/s NRZ Wireline Transceiver With Configurable ADC in 16-nm FinFET.

Parag Upadhyaya, Chi Fung Poon, Siok-Wei Lim, Junho Cho, Arianne Roldan, Wenfeng Zhang, Jin Namkoong, Toan Pham, Bruce Xu, Winson Lin, Hongtao Zhang, Nakul Narang, Kee Hian Tan, Geoff Zhang, Yohan Frans, Ken Chang

IEEE J. Solid State Circuits, 2019

2018

A 112GB/S PAM4 Wireline Receiver Using a 64-Way Time-Interleaved SAR ADC in 16NM FinFET.

James Hudner, Declan Carey, Ronan Casey, Kay Hearne, Pedro Wilson de Abreu Farias Neto, Ilias Chlis, Marc Erett, Chi Fung Poon, Asma Laraba, Hongtao Zhang, Sai Lalith Chaitanya Ambatipudi, David Mahashin, Parag Upadhyaya, Yohan Frans, Ken Chang

Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

A fully adaptive 19-to-56Gb/s PAM-4 wireline transceiver with a configurable ADC in 16nm FinFET.

Parag Upadhyaya, Chi Fung Poon, Siok-Wei Lim, Junho Cho, Arianne Roldan, Wenfeng Zhang, Jin Namkoong, Toan Pham, Bruce Xu, Winson Lin, Hongtao Zhang, Nakul Narang, Kee Hian Tan, Geoff Zhang, Yohan Frans, Ken Chang

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2012

A wide common-mode fully-adaptive multi-standard 12.5Gb/s backplane transceiver in 28nm CMOS.

Jafar Savoj, Kenny C.-H. Hsieh, Parag Upadhyaya, Fu-Tai An, Ade Bekele, Stanley Chen, Xuewen Jiang, Kang Wei Lai, Chi Fung Poon, Aman Sewani, Didem Turker, Karthik Venna, Zhaoyin Daniel Wu, Bruce Xu, Elad Alon, Ken Chang

Proceedings of the Symposium on VLSI Circuits, 2012