Zhaoyin Daniel Wu

According to our database1, Zhaoyin Daniel Wu authored at least 8 papers between 2012 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2022
A 1.24-pJ/b 112-Gb/s (870 Gb/s/Mm) Transceiver for In-Package Links in 7-nm FinFET.
IEEE J. Solid State Circuits, 2022

2021
A 1.24pJ/b 112Gb/s (870Gbps/mm) Transceiver for In-package Links in 7nm FinFET.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

2015
A 0.5-16.3 Gb/s Fully Adaptive Flexible-Reach Transceiver for FPGA in 20 nm CMOS.
IEEE J. Solid State Circuits, 2015

3.3 A 0.5-to-32.75Gb/s flexible-reach wireline transceiver in 20nm CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014
Wideband flexible-reach techniques for a 0.5-16.3Gb/s fully-adaptive transceiver in 20nm CMOS.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013
A Low-Power 0.5-6.6 Gb/s Wireline Transceiver Embedded in Low-Cost 28 nm FPGAs.
IEEE J. Solid State Circuits, 2013

2012
A wide common-mode fully-adaptive multi-standard 12.5Gb/s backplane transceiver in 28nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2012

Design of high-speed wireline transceivers for backplane communications in 28nm CMOS.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012


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