Mark C. Johnson

According to our database1, Mark C. Johnson authored at least 16 papers between 1996 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2021
Modeling and Circuit Analysis of Interconnects with TaS2 Barrier/Liner.
Proceedings of the Device Research Conference, 2021

2019
System-on-a-Chip Design as a Platform for Teaching Design and Design Flow Integration.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

2017
Indiana bicentennial torch project: Trial by fire.
Proceedings of the 2017 IEEE International Conference on Microelectronic Systems Education, 2017

2016
Student use and assessment of System on Chip (SOC) prototyping resource.
Proceedings of the 11th European Workshop on Microelectronics Education, 2016

2015
Satisfying ABET criterion using an industrial Microelectronic Skills Incubator.
Proceedings of the 2015 IEEE International Conference on Microelectronics Systems Education, 2015

2011
Interactive application for learning RTL code structures.
Proceedings of the 2011 IEEE International Conference on Microelectronic Systems Education, 2011

2009
Undergraduate dual-core prototyping and analysis of factors influencing student success on dual-core designs.
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2009

2004
Simultaneous Multiple-Vdd Scheduling and Allocation for Partitioned Floorplan.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

2003
Multiple-Vdd Scheduling/Allocation for Partitioned Floorplan.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

2002
Leakage control with efficient use of transistor stacks in single threshold CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2002

2001
igital Design Education Infrastructure Using Multiple EDA Tool Vendors and Multiple Modes of Tool Access.
Proceedings of the 2001 International Conference on Microelectronics Systems Education, 2001

1999
Design and optimization of dual-threshold circuits for low-voltage low-power applications.
IEEE Trans. Very Large Scale Integr. Syst., 1999

Models and algorithms for bounds on leakage in CMOS circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Leakage Control with Efficient Use of Transistor Stacks in Single Threshold CMOS.
Proceedings of the 36th Conference on Design Automation, 1999

1997
Datapath scheduling with multiple supply voltages and level converters.
ACM Trans. Design Autom. Electr. Syst., 1997

1996
Optimal Selection of Supply Voltages and Level Conversions During Data Path Scheduling Under Resource Constraints.
Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996


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