Yibin Ye

Yang Qin

Pattern Recognit. Lett., 2015

Opportunistic routing with admission control in wireless ad hoc networks.

[BibT_eX]

[DOI]

Comput. Commun., 2015

An environment aware epidemic spreading model and immune strategy in complex networks.

[BibT_eX]

[DOI]

Appl. Math. Comput., 2015

2013

Online sequential extreme learning machine in nonstationary environments.

[BibT_eX]

[DOI]

Neurocomputing, 2013

Learning Capabilities of ELM-Trained Time-Varying Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the Recent Advances of Neural Network Models and Applications, 2013

2011

ELM-based Algorithms for Nonstationary Volterra System Identification.

[BibT_eX]

[DOI]

Proceedings of the Neural Nets WIRN11, 2011

ELM-Based Time-Variant Neural Networks with Incremental Number of Output Basis Functions.

[BibT_eX]

[DOI]

Proceedings of the Advances in Neural Networks - ISNN 2011, 2011

On-Line Extreme Learning Machine for Training Time-Varying Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the Bio-Inspired Computing and Applications, 2011

2010

A Group Selection Evolutionary Extreme Learning Machine approach for Time-Variant Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the Neural Nets WIRN10, 2010

Incremental-Based Extreme Learning Machine Algorithms for Time-Variant Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the Advanced Intelligent Computing Theories and Applications, 2010

2009

Photo Realistic 3D Cartoon Face Modeling Based on Active Shape Model.

[BibT_eX]

[DOI]

Trans. Edutainment, 2009

2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2009

Process, Temperature, and Supply-Noise Tolerant 45nm Dense Cache Arrays With Diffusion-Notch-Free (DNF) 6T SRAM Cells and Dynamic Multi-Vcc Circuits.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2009

EasyFace: a realistic face modeling and facial animation authoring system.

[BibT_eX]

[DOI]

Proceedings of the 8th International Conference on Virtual Reality Continuum and its Applications in Industry, 2009

2008

Skewed Repeater Bus: A Low-Power Scheme for On-Chip Buses.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2008

2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007

A 256-Kb Dual-VCC SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2007

2006

A 4.2GHz 0.3mm2 256kb Dual-Vcc SRAM Building Block in 65nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

Evaluation of differential vs. single-ended sensing and asymmetric cells in 90 nm logic technology for on-chip caches.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005

Skewing adjacent line repeaters to reduce the delay and energy dissipation of on-chip buses.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A Skewed Repeater Bus Architecture for On-Chip Energy Reduction in Microprocessors.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

2004

Design optimizations for microprocessors at low temperature.

[BibT_eX]

[DOI]

Proceedings of the 41th Design Automation Conference, 2004

2003

A 6-GHz 16-kB L1 cache in a 100-nm dual-VT technology using a bitline leakage reduction (BLR) technique.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2003

Dynamic sleep transistor and body bias for active leakage power control of microprocessors.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2003

2002

Analysis of dual-VT SRAM cells with full-swing single-ended bit line sensing for on-chip cache.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2002

5-GHz 32-bit integer execution core in 130-nm dual-VT CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2002

Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors.

[BibT_eX]

[DOI]

Venkatesh Govindarajulu

Vivek De

Shekhar Borkar

Proceedings of the 39th Design Automation Conference, 2002

2001

QSERL: quasi-static energy recovery logic.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2001

2000

Dynamic noise analysis in precharge-evaluate circuits.

[BibT_eX]

[DOI]

Proceedings of the 37th Conference on Design Automation, 2000

1999

Design and optimization of dual-threshold circuits for low-voltage low-power applications.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1999

Mixed-Vth (MVT) CMOS Circuit Design Methodology for Low Power Applications.

[BibT_eX]

[DOI]

Proceedings of the 36th Conference on Design Automation, 1999

Power Consumption in XOR-Based Circuits.

[BibT_eX]

[DOI]

Rolf Drechsler

Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

1998

Estimation of average switching power under accurate modeling of signal correlations.

[BibT_eX]

[DOI]

Zhanping Chen

Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998

1997

Quasi-static energy recovery logic and supply-clock generation circuits.

[BibT_eX]

[DOI]

Georgios I. Stamoulis

Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

A Graph-Based Synthesis Algorithm for AND/XOR Networks.

[BibT_eX]

[DOI]

Proceedings of the 34st Conference on Design Automation, 1997

Efficient synthesis of AND/XOR networks.

[BibT_eX]

[DOI]