Thomas Canhao Xu

According to our database, Thomas Canhao Xu authored at least 40 papers between 2009 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

Deep Belief Network and Closed Polygonal Line for Lung Segmentation in Chest Radiographs.

Tao Peng, Thomas Canhao Xu, Yihuai Wang, Fanzhang Li

Comput. J., 2022

2020

Hybrid Automatic Lung Segmentation on Chest CT Scans.

Tao Peng, Thomas Canhao Xu, Yihuai Wang, Hailing Zhou, Sema Candemir, Wan Mimi Diyana Wan Zaki, Shanq-Jang Ruan, Jing Wang, Xinjian Chen

IEEE Access, 2020

2019

Segmentation of Lung in Chest Radiographs Using Hull and Closed Polygonal Line Method.

Tao Peng, Yihuai Wang, Thomas Canhao Xu, Xinjian Chen

IEEE Access, 2019

2018

Detection of Lung Contour with Closed Principal Curve and Machine Learning.

Tao Peng, Yihuai Wang, Thomas Canhao Xu, Lianmin Shi, Jianwu Jiang, Shilang Zhu

J. Digit. Imaging, 2018

2017

PEN: a power law-enhanced network design for high efficiency multicore architecture.

Thomas Canhao Xu, Ville Leppänen

Concurr. Comput. Pract. Exp., 2017

2016

LUTMap: A Dynamic Heuristic Application Mapping Algorithm Based on Lookup Tables.

Thomas Canhao Xu, Ville Leppänen

Proceedings of the Internet and Distributed Computing Systems, 2016

Analysing and Modelling the On-Chip Traffic of Parallel Applications.

Thomas Canhao Xu, Jonne Pohjankukka, Ville Leppänen

Proceedings of the 42th Euromicro Conference on Software Engineering and Advanced Applications, 2016

2015

PDNOC: Partially diagonal network-on-chip for high efficiency multicore systems.

Thomas Canhao Xu, Ville Leppänen, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen

Concurr. Comput. Pract. Exp., 2015

Parallel Applications and On-chip Traffic Distributions: Observation, Implication and Modelling.

Thomas Canhao Xu, Jonne Pohjankukka, Paavo Nevalainen, Ville Leppänen, Tapio Pahikkala

Proceedings of the ICSOFT-EA 2015, 2015

DBFS: Dual Best-First Search Mapping Algorithm for Shared-Cache Multicore Processors.

Thomas Canhao Xu, Ville Leppänen

Proceedings of the Algorithms and Architectures for Parallel Processing, 2015

Trio: A Triple Class On-chip Network Design for Efficient Multicore Processors.

Thomas Canhao Xu, Ville Leppänen, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen

Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015

Cache- and Communication-aware Application Mapping for Shared-cache Multicore Processors.

Thomas Canhao Xu, Ville Leppänen

Proceedings of the Architecture of Computing Systems - ARCS 2015, 2015

2014

BDMap: A Heuristic Application Mapping Algorithm for the Big Data Era.

Thomas Canhao Xu, Jussi Toivonen, Tapio Pahikkala, Ville Leppänen

Proceedings of the 2014 IEEE 11th Intl Conf on Ubiquitous Intelligence and Computing and 2014 IEEE 11th Intl Conf on Autonomic and Trusted Computing and 2014 IEEE 14th Intl Conf on Scalable Computing and Communications and Its Associated Workshops, 2014

Mixed-Criticality Run-Time Task Mapping for NoC-Based Many-Core Systems.

Mohammad Fattah, Amir-Mohammad Rahmani, Thomas Canhao Xu, Anil Kanduri, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen

Proceedings of the 22nd Euromicro International Conference on Parallel, 2014

Exploration of a Heterogeneous Concentrated-Sparse On-Chip Interconnect for Energy Efficient Multicore Architecture.

Thomas Canhao Xu, Ville Leppänen, Martti Forsell

Proceedings of the 14th IEEE International Conference on Computer and Information Technology, 2014

2013

Optimal placement of vertical connections in 3D Network-on-Chip.

Thomas Canhao Xu, Gert Schley, Pasi Liljeberg, Martin Radetzki, Juha Plosila, Hannu Tenhunen

J. Syst. Archit., 2013

PDNOC: An Efficient Partially Diagonal Network-on-Chip Design.

Thomas Canhao Xu, Ville Leppänen, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen

Proceedings of the Parallel Processing and Applied Mathematics, 2013

OPTNOC: An Optimized 3D Network-on-Chip Design for Fast Memory Access.

Thomas Canhao Xu, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen

Proceedings of the Parallel Computing Technologies - 12th International Conference, 2013

Evaluate and optimize parallel Barnes-Hut algorithm for emerging many-core architectures.

Thomas Canhao Xu, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen

Proceedings of the International Conference on High Performance Computing & Simulation, 2013

DSNOC: A Hybrid Dense-Sparse Network-on-Chip Architecture for Efficient Scalable Computing.

Thomas Canhao Xu, Ville Leppänen, Martti Forsell

Proceedings of the IEEE 11th International Conference on Dependable, 2013

Optimized multicore architectures for data parallel fast Fourier transform.

Thomas Canhao Xu, Tapio Pahikkala, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen

Proceedings of the Computer Systems and Technologies, 2013

MMSoC: a multi-layer multi-core storage-on-chip design for systems with high integration.

Thomas Canhao Xu, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen

Proceedings of the Computer Systems and Technologies, 2013

2012

Parallelized Online Regularized Least-Squares for Adaptive Embedded Systems.

Tapio Pahikkala, Antti Airola, Thomas Canhao Xu, Pasi Liljeberg, Hannu Tenhunen, Tapio Salakoski

Int. J. Embed. Real Time Commun. Syst., 2012

Exploration of heuristic scheduling algorithms for 3D multicore processors.

Thomas Canhao Xu, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen

Proceedings of the Workshop on Software and Compilers for Embedded Systems, 2012

A high-efficiency low-cost heterogeneous 3D network-on-chip design.

Thomas Canhao Xu, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen

Proceedings of the Fifth International Workshop on Network on Chip Architectures, 2012

Implementation and Analysis of Block Dense Matrix Decomposition on Network-on-Chips.

Thomas Canhao Xu, Tapio Pahikkala, Antti Airola, Pasi Liljeberg, Juha Plosila, Tapio Salakoski, Hannu Tenhunen

Proceedings of the 14th IEEE International Conference on High Performance Computing and Communication & 9th IEEE International Conference on Embedded Software and Systems, 2012

2011

A study of 3D Network-on-Chip design for data parallel H.264 coding.

Thomas Canhao Xu, Alexander Wei Yin, Pasi Liljeberg, Hannu Tenhunen

Microprocess. Microsystems, 2011

A generic adaptive path-based routing method for MPSoCs.

Masoud Daneshtalab, Masoumeh Ebrahimi, Thomas Canhao Xu, Pasi Liljeberg, Hannu Tenhunen

J. Syst. Archit., 2011

A Parallel Online Regularized Least-squares Machine Learning Algorithm for Future Multi-core Processors.

Tapio Pahikkala, Antti Airola, Thomas Canhao Xu, Pasi Liljeberg, Hannu Tenhunen, Tapio Salakoski

Proceedings of the PECCS 2011, 2011

Explorations of optimal core and cache placements for Chip Multiprocessor.

Thomas Canhao Xu, Pasi Liljeberg, Hannu Tenhunen

Proceedings of the 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, 2011

A Minimal Average Accessing Time Scheduler for Multicore Processors.

Thomas Canhao Xu, Pasi Liljeberg, Hannu Tenhunen

Proceedings of the Algorithms and Architectures for Parallel Processing, 2011

Process scheduling for future multicore processors.

Thomas Canhao Xu, Pasi Liljeberg, Hannu Tenhunen

Proceedings of the Fifth International Workshop on Interconnection Network Architecture, 2011

Study of Hierarchical N-Body Methods for Network-on-Chip Architectures.

Thomas Canhao Xu, Pasi Liljeberg, Hannu Tenhunen

Proceedings of the Euro-Par 2011: Parallel Processing Workshops - CCPI, CGWS, HeteroPar, HiBB, HPCVirt, HPPC, HPSS, MDGS, ProPer, Resilience, UCHPC, VHPC, Bordeaux, France, August 29, 2011

Optimal number and placement of Through Silicon Vias in 3D Network-on-Chip.

Thomas Canhao Xu, Pasi Liljeberg, Hannu Tenhunen

Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

Optimal memory controller placement for chip multiprocessor.

Thomas Canhao Xu, Pasi Liljeberg, Hannu Tenhunen

Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

Change Function of 2D/3D Network-on-Chip.

Alexander Wei Yin, Thomas Canhao Xu, Bo Yang, Pasi Liljeberg, Hannu Tenhunen

Proceedings of the 11th IEEE International Conference on Computer and Information Technology, 2011

2010

A Greedy Heuristic Approximation Scheduling Algorithm for 3D Multicore Processors.

Thomas Canhao Xu, Pasi Liljeberg, Hannu Tenhunen

Proceedings of the Euro-Par 2011: Parallel Processing Workshops - CCPI, CGWS, HeteroPar, HiBB, HPCVirt, HPPC, HPSS, MDGS, ProPer, Resilience, UCHPC, VHPC, Bordeaux, France, August 29, 2010

Tree-model based mapping for energy-efficient and low-latency Network-on-Chip.

Bo Yang, Thomas Canhao Xu, Tero Säntti, Juha Plosila

Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

Operating System Processor Scheduler Design for Future Chip Multiprocessor.

Thomas Canhao Xu, Alexander Wei Yin, Pasi Liljeberg, Hannu Tenhunen

Proceedings of the ARCS '10, 2010

2009

Explorations of Honeycomb Topologies for Network-on-Chip.

Alexander Wei Yin, Thomas Canhao Xu, Pasi Liljeberg, Hannu Tenhunen

Proceedings of the NPC 2009, 2009