Mason Chern

According to our database¹, Mason Chern authored at least 9 papers between 2017 and 2023.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

Timeline

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Bibliography

2023

Diagnosis of Systematic Delay Failures Through Subset Relationship Analysis.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2023

2022

Diagnosing Double Faulty Chains through Failing Bit Separation.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2022

2021

Identifying Good-Dice-in-Bad-Neighborhoods Using Artificial Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 39th IEEE VLSI Test Symposium, 2021

2020

Diagnosis of Intermittent Scan Chain Faults Through a Multistage Neural Network Reasoning Process.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

CNN-based Stochastic Regression for IDDQ Outlier Identification.

[BibT_eX]

[DOI]

Proceedings of the 38th IEEE VLSI Test Symposium, 2020

2019

Layout-Based Dual-Cell-Aware Tests.

[BibT_eX]

[DOI]

Proceedings of the 37th IEEE VLSI Test Symposium, 2019

Methodology of Generating Timing-Slack-Based Cell-Aware Tests.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2019

Improving scan chain diagnostic accuracy using multi-stage artificial neural networks.

[BibT_eX]

[DOI]

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2017

Resilient Cell-Based Architecture for Time-to-Digital Converter.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Mason Chern

Timeline

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