Hamid Noori
Orcid: 0000-0003-1410-6781
According to our database1,
Hamid Noori
authored at least 58 papers
between 1990 and 2022.
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Bibliography
2022
Online energy-efficient fair scheduling for heterogeneous multi-cores considering shared resource contention.
J. Supercomput., 2022
Characterizing energy and performance of soft-core-based homogeneous multiprocessor systems.
J. Supercomput., 2022
2021
J. Supercomput., 2021
IEEE Trans. Computers, 2021
A novel approach based on genetic algorithm to speed up the discovery of classification rules on GPUs.
Knowl. Based Syst., 2021
2020
IEEE Trans. Parallel Distributed Syst., 2020
2019
2017
Performance evaluation metrics for ring-oscillator-based temperature sensors on FPGAs: A quality factor.
Integr., 2017
Proceedings of the Applied Reconfigurable Computing - 13th International Symposium, 2017
2016
J. Parallel Distributed Comput., 2016
Eur. J. Oper. Res., 2016
2015
Critical path-aware voltage island partitioning and floorplanning for hard real-time embedded systems.
Integr., 2015
Strategizing niceness in co-opetition: The case of knowledge exchange in supply chain innovation projects.
Eur. J. Oper. Res., 2015
Dynamic Task Priority Scaling for Thermal Management of Multi-core Processors with Heavy Workload.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015
Exploring Efficiency of Ring Oscillator-Based Temperature Sensor Networks on FPGAs (Abstract Only).
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015
2014
Proactive task migration with a self-adjusting migration threshold for dynamic thermal management of multi-core processors.
J. Supercomput., 2014
Scenario-based quasi-static task mapping and scheduling for temperature-efficient MPSoC design under process variation.
Microprocess. Microsystems, 2014
High-level design space exploration of locally linear neuro-fuzzy models for embedded systems.
Fuzzy Sets Syst., 2014
A neuro-fuzzy fan speed controller for dynamic thermal management of multi-core processors.
Proceedings of the Computing Frontiers Conference, CF'14, 2014
Physical-aware task migration algorithm for dynamic thermal management of SMT multi-core processors.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
A new merit function for custom instruction selection under an area budget constraint.
Des. Autom. Embed. Syst., 2013
Proceedings of the East-West Design & Test Symposium, 2013
2012
Improving performance and energy efficiency of embedded processors via post-fabrication instruction set customization.
J. Supercomput., 2012
A new methodology for evaluating sustainable product design performance with two-stage network data envelopment analysis.
Eur. J. Oper. Res., 2012
2011
Software-Level Instruction-Cache Leakage Reduction Using Value-Dependence of SRAM Leakage in Nanometer Technologies.
Trans. High Perform. Embed. Archit. Compil., 2011
Securing Embedded Processors against Power Analysis Based Side Channel Attacks Using Reconfigurable Architecture.
Proceedings of the IEEE/IFIP 9th International Conference on Embedded and Ubiquitous Computing, 2011
Instruction and data cache peak temperature reduction using cache access balancing in embedded processors.
Proceedings of the 9th IEEE/ACS International Conference on Computer Systems and Applications, 2011
2010
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010
A novel high speed residue to binary converter design based on the three-moduli set {2<sup>n</sup>, 2<sup>n+1</sup>+1, 2<sup>n+1</sup>-1}.
Proceedings of the 2010 East-West Design & Test Symposium, 2010
Dual-purpose custom instruction identification algorithm based on Particle Swarm Optimization.
Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010
2009
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
A combined analytical and simulation-based model for performance evaluation of a reconfigurable instruction set processor.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
J. Supercomput., 2008
A Reconfigurable Functional Unit with Conditional Execution for Multi-Exit Custom Instructions.
IEICE Trans. Electron., 2008
IEICE Trans. Electron., 2008
Improving Energy Efficiency of Configurable Caches via Temperature-Aware Configuration Selection.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008
Enhancing energy efficiency of processor-based embedded systems through post-fabrication ISA extension.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008
Variation-Aware Software Techniques for Cache Leakage Reduction Using Value-Dependence of SRAM Leakage Due to Within-Die Process Variation.
Proceedings of the High Performance Embedded Architectures and Compilers, 2008
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
2007
Building an adaptive manufacturing enterprise for the Hong Kong watchmaking industry.
Int. J. Manuf. Technol. Manag., 2007
Improving Performance and Energy Saving in a Reconfigurable Processor via Accelerating Control Data Flow Graphs.
IEICE Trans. Inf. Syst., 2007
Proceedings of the Embedded Software and Systems, [Third] International Conference, 2007
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
Interactive presentation: Generating and executing multi-exit custom instructions for an adaptive extensible processor.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
The Effect of Nanometer-Scale Technologies on the Cache Size Selection for Low Energy Embedded Systems.
Proceedings of the 2007 International Conference on Embedded Systems & Applications, 2007
2006
Preliminary performance evaluation of an adaptive dynamic extensible processor for embedded applications.
Proceedings of the 2006 ACM Symposium on Applied Computing (SAC), 2006
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006
Custom Instruction Generation Using Temporal Partitioning Techniques for a Reconfigurable Functional Unit.
Proceedings of the Embedded and Ubiquitous Computing, International Conference, 2006
GifT: A Gravity-Directed and Life-Time Based Algorithm for Temporal Partitioning of Data Flow Graphs.
Proceedings of the 2006 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2006
An Integrated Temporal Partitioning and Mapping Framework for Handling Custom Instructions on a Reconfigurable Functional Unit.
Proceedings of the Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, 2006
2005
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005
2002
Int. J. Manuf. Technol. Manag., 2002
2001
Proceedings of the Field-Programmable Logic and Applications, 2001
1990