Ronald G. Dreslinski
Orcid: 0000-0003-4188-4650Affiliations:
- University of Michigan, Ann Arbor, USA
According to our database1,
Ronald G. Dreslinski
authored at least 143 papers
between 2005 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on orcid.org
On csauthors.net:
Bibliography
2024
IEEE Des. Test, February, 2024
2023
AnGeL: Fully-Automated Analog Circuit Generator Using a Neural Network Assisted Semi-Supervised Learning Approach.
IEEE Trans. Circuits Syst. I Regul. Pap., November, 2023
Proc. VLDB Endow., November, 2023
CrossTalk: Making Low-Latency Fault Tolerance Cheap by Exploiting Redundant Networks.
ACM Trans. Embed. Comput. Syst., October, 2023
Open Information Extraction: A Review of Baseline Techniques, Approaches, and Applications.
CoRR, 2023
Accelerating Graph Analytics on a Reconfigurable Architecture with a Data-Indirect Prefetcher.
CoRR, 2023
Proceedings of the 44th IEEE Symposium on Security and Privacy, 2023
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023
FuNToM: Functional Modeling of RF Circuits Using a Neural Network Assisted Two-Port Analysis Method.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
Chex-Mix: Combining Homomorphic Encryption with Trusted Execution Environments for Oblivious Inference in the Cloud.
Proceedings of the 8th IEEE European Symposium on Security and Privacy, 2023
GRACE: A Scalable Graph-Based Approach to Accelerating Recommendation Model Inference.
Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023
2022
ACM Trans. Storage, 2022
IEEE Trans. Intell. Transp. Syst., 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Versa: A 36-Core Systolic Multiprocessor With Dynamically Reconfigurable Interconnect and Memory.
IEEE J. Solid State Circuits, 2022
ACM J. Emerg. Technol. Comput. Syst., 2022
CoRR, 2022
A 507 GMACs/J 256-Core Domain Adaptive Systolic-Array-Processor for Wireless Communication and Linear-Algebra Kernels in 12nm FINFET.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022
A Unified Forward Error Correction Accelerator for Multi-Mode Turbo, LDPC, and Polar Decoding.
Proceedings of the ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1, 2022
Improving Energy Efficiency of Convolutional Neural Networks on Multi-core Architectures through Run-time Reconfiguration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Enabling Software-Defined RF Convergence with a Novel Coarse-Scale Heterogeneous Processor.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022
MeNDA: a near-memory multi-way merge solution for sparse transposition and dataflows.
Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
Squaring the circle: Executing Sparse Matrix Computations on FlexTPU - A TPU-Like Processor.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2022
Locality-Aware Optimizations for Improving Remote Memory Latency in Multi-GPU Systems.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2022
2021
Applications of Artificial Intelligence on the Modeling and Optimization for Analog and Mixed-Signal Circuits: A Review.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
An Ultra-Low-Power Image Signal Processor for Hierarchical Image Recognition With Deep Neural Networks.
IEEE J. Solid State Circuits, 2021
A Survey Describing Beyond Si Transistors and Exploring Their Implications for Future Processors.
ACM J. Emerg. Technol. Comput. Syst., 2021
CHEX-MIX: Combining Homomorphic Encryption with Trusted Execution Environments for Two-party Oblivious Inference in the Cloud.
IACR Cryptol. ePrint Arch., 2021
F1: A Fast and Programmable Accelerator for Fully Homomorphic Encryption (Extended Version).
CoRR, 2021
IEEE Comput. Archit. Lett., 2021
Versa: A Dataflow-Centric Multiprocessor with 36 Systolic ARM Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28nm.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
Improving Performance of Flash Based Key-Value Stores Using Storage Class Memory as a Volatile Memory Extension.
Proceedings of the 2021 USENIX Annual Technical Conference, 2021
RISC-V Reward: Building Out-of-Order Processors in a Computer Architecture Design Course with an Open-Source ISA.
Proceedings of the SIGCSE '21: The 52nd ACM Technical Symposium on Computer Science Education, 2021
IGOR: Accelerating Byzantine Fault Tolerance for Real-Time Systems with Eager Execution.
Proceedings of the 27th IEEE Real-Time and Embedded Technology and Applications Symposium, 2021
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021
SparseAdapt: Runtime Control for Sparse Linear Algebra on a Reconfigurable Accelerator.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021
Proceedings of the IEEE International Symposium on Workload Characterization, 2021
Prodigy: Improving the Memory Latency of Data-Indirect Irregular Workloads Using Hardware-Software Co-Design.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
2020
Tetris: Using Software/Hardware Co-Design to Enable Handheld, Physics-Limited 3D Plane-Wave Ultrasound Imaging.
IEEE Trans. Computers, 2020
A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix-Matrix Multiplication Accelerator.
IEEE J. Solid State Circuits, 2020
IACR Cryptol. ePrint Arch., 2020
STOMP: A Tool for Evaluation of Scheduling Policies in Heterogeneous Multi-Processors.
CoRR, 2020
A 170μW Image Signal Processor Enabling Hierarchical Image Recognition for Intelligence at the Edge.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
Fully-Autonomous SoC Synthesis Using Customizable Cell-Based Analog and Mixed-Signal Circuits Generation.
Proceedings of the VLSI-SoC: Design Trends, 2020
Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2020
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2020
Accelerating Deep Neural Network Computation on a Low Power Reconfigurable Architecture.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
HETSIM: Simulating Large-Scale Heterogeneous Systems using a Trace-driven, Synchronization and Dependency-Aware Framework.
Proceedings of the IEEE International Symposium on Workload Characterization, 2020
Proceedings of the ICS '20: 2020 International Conference on Supercomputing, 2020
Accelerating Linear Algebra Kernels on a Massively Parallel Reconfigurable Architecture.
Proceedings of the 2020 IEEE International Conference on Acoustics, 2020
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
Proceedings of the PACT '20: International Conference on Parallel Architectures and Compilation Techniques, 2020
2019
A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
Proceedings of the International Symposium on Memory Systems, 2019
Proceedings of the 2019 IEEE Intelligent Transportation Systems Conference, 2019
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2019
3DTUBE: A Design Framework for High-Variation Carbon Nanotube-based Transistor Technology.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019
Tetris: A Streaming Accelerator for Physics-Limited 3D Plane-Wave Ultrasound Imaging.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
2018
The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips.
IEEE Micro, 2018
A 1920 × 1080 30-frames/s 2.3 TOPS/W Stereo-Depth Processor for Energy-Efficient Autonomous Navigation of Micro Aerial Vehicles.
IEEE J. Solid State Circuits, 2018
Proceedings of the International Symposium on Memory Systems, 2018
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018
2017
Reining in Long Tails in Warehouse-Scale Computers with Quick Voltage Boosting Using Adrenaline.
ACM Trans. Comput. Syst., 2017
3.7 A 1920×1080 30fps 2.3TOPS/W stereo-depth processor for robust autonomous navigation.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
14.7 A 288µW programmable deep-learning processor with 270KB on-chip weight storage using non-uniform memory hierarchy for mobile intelligence.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017
Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017
2016
Designing Future Warehouse-Scale Computers for Sirius, an End-to-End Voice and Vision Personal Assistant.
ACM Trans. Comput. Syst., 2016
IEEE Trans. Computers, 2016
IEEE Micro, 2016
Energy-Autonomous Wireless Communication for Millimeter-Scale Internet-of-Things Sensor Nodes.
IEEE J. Sel. Areas Commun., 2016
Proceedings of the Second International Symposium on Memory Systems, 2016
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016
Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016
Near-threshold computing in FinFET technologies: opportunities for improved voltage scalability.
Proceedings of the 53rd Annual Design Automation Conference, 2016
2015
J. Signal Process. Syst., 2015
Proceedings of the 48th International Symposium on Microarchitecture, 2015
Proceedings of the 2015 IEEE International Symposium on Performance Analysis of Systems and Software, 2015
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015
DjiNN and Tonic: DNN as a service and its implications for future warehouse scale computers.
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015
Sirius: An Open End-to-End Voice and Vision Personal Assistant and Its Implications for Future Warehouse Scale Computers.
Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems, 2015
2014
Evaluating private vs. shared last-level caches for energy efficiency in asymmetric multi-cores.
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014
Proceedings of the 2014 IEEE International Symposium on Performance Analysis of Systems and Software, 2014
Proceedings of the 2014 IEEE International Symposium on Performance Analysis of Systems and Software, 2014
Proceedings of the IEEE International Conference on Acoustics, 2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
Integrated 3D-stacked server designs for increasing physical density of key-value stores.
Proceedings of the Architectural Support for Programming Languages and Operating Systems, 2014
Proceedings of the International Conference on Parallel Architectures and Compilation, 2014
2013
Centip3De: A Cluster-Based NTC Architecture With 64 ARM Cortex-M3 Cores in 3D Stacked 130 nm CMOS.
IEEE J. Solid State Circuits, 2013
Centip3De: a many-core prototype exploring 3D integration and near-threshold computing.
Commun. ACM, 2013
Proceedings of the IEEE Workshop on Signal Processing Systems, 2013
Proceedings of the International Conference for High Performance Computing, 2013
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013
Parallelization techniques for implementing trellis algorithms on graphics processors.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013
Proceedings of the IEEE International Symposium on Workload Characterization, 2013
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013
2012
IEEE J. Emerg. Sel. Topics Circuits Syst., 2012
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012
A 4.5Tb/s 3.4Tb/s/W 64×64 switch fabric with self-updating least-recently-granted priority and quality-of-service arbitration in 45nm CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
Centip3De: A 3930DMIPS/W configurable near-threshold 3D stacked system with 64 ARM Cortex-M3 cores.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
Proceedings of the 30th International IEEE Conference on Computer Design, 2012
Proceedings of the 2012 IEEE Hot Chips 24 Symposium (HCS), 2012
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
High radix self-arbitrating switch fabric with multiple arbitration schemes and quality of service.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
Proceedings of the 15th International Conference on Compilers, 2012
XPoint cache: scaling existing bus-based coherence protocols for 2D and 3D many-core systems.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012
2011
Near Threshold Computing: From Single Core to Many-Core Energy Efficient Architectures.
PhD thesis, 2011
Proceedings of the 2011 IEEE International Symposium on Workload Characterization, 2011
Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011
Proceedings of the Design, Automation and Test in Europe, 2011
2010
Near-Threshold Computing: Reclaiming Moore's Law Through Energy Efficient Integrated Circuits.
Proc. IEEE, 2010
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010
Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010
2009
Proceedings of the Embedded Computer Systems: Architectures, 2009
Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009
2008
Energy-Efficient Simultaneous Thread Fetch from Different Cache Levels in a Soft Real-Time SMT Processor.
Proceedings of the Embedded Computer Systems: Architectures, 2008
Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), 2008
2007
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007
Proceedings of the 4th Conference on Computing Frontiers, 2007
Proceedings of the 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), 2007
2006
PicoServer: using 3D stacking technology to enable a compact energy efficient chip multiprocessor.
Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, 2006
2005
Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques (PACT 2005), 2005