Midia Reshadi

Orcid: 0000-0001-7628-2401

According to our database1, Midia Reshadi authored at least 77 papers between 2008 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Implicit Lightweight Proxy Based Key Agreement for the Internet of Things (ILPKA).
Wirel. Pers. Commun., June, 2023

Optimized reverse converters with multibit soft error correction support at 7nm technology.
Comput. Electr. Eng., April, 2023

Energy management of fault-tolerant real-time embedded systems through switching-activity-based techniques.
Microprocess. Microsystems, 2023

An energy-aware scheme for solving the routing problem in the internet of things based on jaya and flower pollination algorithms.
J. Ambient Intell. Humaniz. Comput., 2023

Low-cost regional-based congestion-aware routing algorithm for 2D mesh NoC.
Int. J. Commun. Syst., 2023

Maple: A Processing Element for Row-Wise Product Based Sparse Tensor Accelerators.
CoRR, 2023

Dynamic Resource Partitioning for Multi-Tenant Systolic Array Based DNN Accelerator.
Proceedings of the 31st Euromicro International Conference on Parallel, 2023

2022
An Energy-Aware IoT Routing Approach Based on a Swarm Optimization Algorithm and a Clustering Technique.
Wirel. Pers. Commun., 2022

An energy-aware clustering method in the IoT using a swarm-based algorithm.
Wirel. Networks, 2022

Mapping and virtual neuron assignment algorithms for MAERI accelerator.
J. Supercomput., 2022

Visible light communication networks MAC layer solutions: open issues and trends.
Photonic Netw. Commun., 2022

Reconfigurable Network-on-Chip based Convolutional Neural Network Accelerator.
J. Syst. Archit., 2022

A new clustering-based routing method in the mobile internet of things using a krill herd algorithm.
Clust. Comput., 2022

MCPS: a mapping method for MAERI accelerator base on Cartesian Product based Convolution for DNN layers with sparse input feature map.
Clust. Comput., 2022

2021
Efficient designs of reversible sequential circuits.
J. Supercomput., 2021

Efficient binary to quaternary and vice versa converters: embedding in quaternary arithmetic circuits.
J. Supercomput., 2021

Efficient techniques for fault detection and location of multiple controlled Toffoli-based reversible circuit.
Quantum Inf. Process., 2021

Blind separation of underdetermined Convolutive speech mixtures by time-frequency masking with the reduction of musical noise of separated signals.
Multim. Tools Appl., 2021

Determining the Parameters of DBSCAN Automatically Using the Multi-Objective Genetic Algorithm.
J. Inf. Sci. Eng., 2021

A New Preventive Routing Method Based on Clustering and Location Prediction in the Mobile Internet of Things.
IEEE Internet Things J., 2021

Clustered Routing Method in the Internet of Things Using a Moth-Flame Optimization Algorithm.
Int. J. Commun. Syst., 2021

A novel arbitration mechanism for crossbar switch in wireless network-on-chip.
Clust. Comput., 2021

Data scheduling and placement in deep learning accelerator.
Clust. Comput., 2021

An accurate model to predict the performance of graphical processors using data mining and regression theory.
Comput. Electr. Eng., 2021

SID-Mesh: Diagonal Mesh Topology for Silicon Interposer in 2.5D NoC with Introducing a New Routing Algorithm.
Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2021

LOCAL: Low-Complex Mapping Algorithm for Spatial DNN Accelerators.
Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2021, Oslo, 2021

2020
Improving the Network Life Time in Smart Grid Sensor Nodes by Considering Nodes Usage.
SN Comput. Sci., January, 2020

Management of Load-Balancing Data Stream in Interposer-Based Network-on-Chip Using Specific Virtual Channels.
Wirel. Commun. Mob. Comput., 2020

Designing a MapReduce performance model in distributed heterogeneous platforms based on benchmarking approach.
J. Supercomput., 2020

A survey and taxonomy of congestion control mechanisms in wireless network on chip.
J. Syst. Archit., 2020

Special issue on energy-efficient many-core embedded systems and architectures (SI: NoCArc18).
J. Syst. Archit., 2020

Flow mapping on mesh-based deep learning accelerator.
J. Parallel Distributed Comput., 2020

WidePLive: a coupled low-delay overlay construction mechanism and peer-chunk priority-based chunk scheduling for P2P live video streaming.
IET Commun., 2020

Flow control and scheduling mechanism to improve network performance in wireless NoC.
IET Commun., 2020

Efficient design of quaternary quantum comparator with only a single ancillary input.
IET Circuits Devices Syst., 2020

Efficient Designs of Reversible Majority Voters.
J. Electron. Test., 2020

Novel Optimum Parity-Preserving Reversible Multiplier Circuits.
Circuits Syst. Signal Process., 2020

Comprehensive regression-based model to predict performance of general-purpose graphics processing unit.
Clust. Comput., 2020

Network adapter architectures in network on chip: comprehensive literature review.
Clust. Comput., 2020

CACBR: Congestion Aware Cluster Buffer base routing algorithm with minimal cost on NOC.
CCF Trans. High Perform. Comput., 2020

2019
Decreasing latency considering power consumption issue in silicon interposer-based network-on-chip.
J. Supercomput., 2019

CLBM: Controlled load-balancing mechanism for congestion management in silicon interposer NoC architecture.
J. Syst. Archit., 2019

HybSMRP: a hybrid scheduling algorithm in Hadoop MapReduce framework.
J. Big Data, 2019

DICA: destination intensity and congestion-aware output selection strategy for network-on-chip systems.
IET Comput. Digit. Tech., 2019

An expandable topology with low wiring congestion for silicon interposer-based network-on-chip systems.
Trans. Emerg. Telecommun. Technol., 2019

Flow mapping and data distribution on mesh-based deep learning accelerator.
Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip, 2019

2018
A deadlock-free routing algorithm for irregular 3D network-on-chips with wireless links.
J. Supercomput., 2018

Application mapping in hybrid photonic networks-on-chip for reducing insertion loss.
J. Supercomput., 2018

ReDePoly: reducing delays in multi-channel P2P live streaming systems using distributed intelligence.
Telecommun. Syst., 2018

Reducing bypass-based network-on-chip latency using priority mechanism.
IET Comput. Digit. Tech., 2018

Application partitioning and mapping for bypass channel based NoC.
Comput. Electr. Eng., 2018

Reconfigurable Network-on-Chip for 3D Neural Network Accelerators.
Proceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip, 2018

Security Improvement of FPGA Design Against Timing Side Channel Attack Using Dynamic Delay Management.
Proceedings of the 2018 IEEE Canadian Conference on Electrical & Computer Engineering, 2018

2017
A Novel Many-Objective Clustering Algorithm in Mobile Ad Hoc Networks.
Wirel. Pers. Commun., 2017

A heuristic clustering approach to use case-aware application-specific network-on-chip synthesis.
J. Supercomput., 2017

Erratum to: Loss-aware routing algorithm for photonic networks on chip.
J. Supercomput., 2017

Loss-aware routing algorithm for photonic networks on chip.
J. Supercomput., 2017

Mapping multiple applications onto 3D NoC-based MPSoCs supporting wireless links.
J. Supercomput., 2017

The cost-effective fault detection and fault location approach for communication channels in NoC.
J. Supercomput., 2017

A routing algorithm for reducing optical loss in photonic Networks-on-Chip.
Photonic Netw. Commun., 2017

InFreD: Intelligent Free Rider Detection in collaborative distributed systems.
J. Netw. Comput. Appl., 2017

A New BIST-based Test Approach with the Fault Location Capability for Communication Channels in Network-on-Chip.
J. Electron. Test., 2017

Link Testing: a Survey of Current Trends in Network on Chip.
J. Electron. Test., 2017

2016
Performance evaluation of task migration in contiguous allocation for mesh interconnection topology.
J. Supercomput., 2016

Loss-Aware Switch Design and Non-Blocking Detection Algorithm for Intra-Chip Scale Photonic Interconnection Networks.
IEEE Trans. Computers, 2016

AMAP: a new heuristic communication-aware tasks mapping onto 2D mesh NoCs.
Proceedings of the 24th High Performance Computing Symposium, 2016

Aspect and distance based NoC mapping (ADB).
Proceedings of the 8th International Symposium on Telecommunications, 2016

XY-axis and distance based NoC mapping (XY-ADB).
Proceedings of the 8th International Symposium on Telecommunications, 2016

2015
A Reader Anti-collision Protocol for RFID-Enhanced Wireless Sensor Networks.
Wirel. Pers. Commun., 2015

A low-cost and latency bypass channel-based on-chip network.
J. Supercomput., 2015

2014
Performance improvement of application-specific network on chip using machine learning algorithms.
Int. J. High Perform. Syst. Archit., 2014

2013
A fault tolerant approach for application-specific Network-on-Chip.
Proceedings of the 2013 NORCHIP, Vilnius, Lithuania, November 11-12, 2013, 2013

2012
PathAware: A contention-aware selection function for application-specific Network-On-Chips.
Proceedings of the NORCHIP 2012, Copenhagen, Denmark, November 12-13, 2012, 2012

CoolMap: A Thermal-Aware Mapping Algorithm for Application Specific Networks-on-Chip.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

2011
Yield modeling and yield-aware mapping for application specific networks-on-chip.
Proceedings of the 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, 2011

2010
Elixir: A new bandwidth-constrained mapping for Networks-on-chip.
IEICE Electron. Express, 2010

2008
Reliable and Secure Chip Level Communication by residue number System Code.
Trans. SDPS, 2008


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