Mihir R. Choudhury

According to our database, Mihir R. Choudhury authored at least 25 papers between 2005 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2021

Project CodeNet: A Large-Scale AI for Code Dataset for Learning a Diversity of Coding Tasks.

Ruchir Puri, David S. Kung, Geert Janssen, Wei Zhang, Giacomo Domeniconi, Vladimir Zolotov, Julian Dolby, Jie Chen, Mihir R. Choudhury, Lindsey Decker, Veronika Thost, Luca Buratti, Saurabh Pujar, Ulrich Finkler

CoRR, 2021

CodeNet: A Large-Scale AI for Code Dataset for Learning a Diversity of Coding Tasks.

Ruchir Puri, David S. Kung, Geert Janssen, Wei Zhang, Giacomo Domeniconi, Vladimir Zolotov, Julian Dolby, Jie Chen, Mihir R. Choudhury, Lindsey Decker, Veronika Thost, Luca Buratti, Saurabh Pujar, Shyam Ramji, Ulrich Finkler, Susan Malaika, Frederick Reiss

Proceedings of the Neural Information Processing Systems Track on Datasets and Benchmarks 1, 2021

2019

NeuNetS: An Automated Synthesis Engine for Neural Network Design.

Atin Sood, Benjamin Elder, Benjamin Herta, Chao Xue, Costas Bekas, A. Cristiano I. Malossi, Debashish Saha, Florian Scheidegger, Ganesh Venkataraman, Gegi Thomas, Giovanni Mariani, Hendrik Strobelt, Horst Samulowitz, Martin Wistuba, Matteo Manica, Mihir R. Choudhury, Rong Yan, Roxana Istrate, Ruchir Puri, Tejaswini Pedapati

CoRR, 2019

2016

Polynomial Time Algorithm for Area and Power Efficient Adder Synthesis in High-Performance Designs.

Subhendu Roy, Mihir R. Choudhury, Ruchir Puri, David Z. Pan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

2014

Towards Optimal Performance-Area Trade-Off in Adders by Synthesis of Parallel Prefix Structures.

Subhendu Roy, Mihir R. Choudhury, Ruchir Puri, David Z. Pan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Time-Borrowing Circuit Designs and Hardware Prototyping for Timing Error Resilience.

Mihir R. Choudhury, Vikas Chandra, Robert C. Aitken, Kartik Mohanram

IEEE Trans. Computers, 2014

Bridging high performance and low power in processor design.

Ruchir Puri, Mihir R. Choudhury, Haifeng Qian, Matthew M. Ziegler

Proceedings of the International Symposium on Low Power Electronics and Design, 2014

2013

Low Cost Concurrent Error Masking Using Approximate Logic Circuits.

Mihir R. Choudhury, Kartik Mohanram

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

2011

Reliability-driven don't care assignment for logic synthesis.

Andrew Zukoski, Mihir R. Choudhury, Kartik Mohanram

Proceedings of the Design, Automation and Test in Europe, 2011

2010

Bi-decomposition of large Boolean functions using blocking edge graphs.

Mihir R. Choudhury, Kartik Mohanram

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Dominant critical gate identification for power and yield optimization in logic circuits.

Mihir R. Choudhury, Masoud Rostami, Kartik Mohanram

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

TIMBER: Time borrowing and error relaying for online timing error resilience.

Mihir R. Choudhury, Vikas Chandra, Kartik Mohanram, Robert C. Aitken

Proceedings of the Design, Automation and Test in Europe, 2010

Analytical model for TDDB-based performance degradation in combinational logic.

Mihir R. Choudhury, Vikas Chandra, Kartik Mohanram, Robert C. Aitken

Proceedings of the Design, Automation and Test in Europe, 2010

2009

Reliability Analysis of Logic Circuits.

Mihir R. Choudhury, Kartik Mohanram

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Soft Error Rate Reduction Using Circuit Optimization and Transient Filter Insertion.

Mihir R. Choudhury, Quming Zhou, Kartik Mohanram

J. Electron. Test., 2009

Masking timing errors on speed-paths in logic circuits.

Mihir R. Choudhury, Kartik Mohanram

Proceedings of the Design, Automation and Test in Europe, 2009

Timing-driven optimization using lookahead logic circuits.

Mihir R. Choudhury, Kartik Mohanram

Proceedings of the 46th Design Automation Conference, 2009

2008

Tunable Transient Filters for Soft Error Rate Reduction in Combinational Circuits.

Quming Zhou, Mihir R. Choudhury, Kartik Mohanram

Proceedings of the 13th European Test Symposium, 2008

Approximate logic circuits for low overhead, non-intrusive concurrent error detection.

Mihir R. Choudhury, Kartik Mohanram

Proceedings of the Design, Automation and Test in Europe, 2008

Technology exploration for graphene nanoribbon FETs.

Mihir R. Choudhury, Youngki Yoon, Jing Guo, Kartik Mohanram

Proceedings of the 45th Design Automation Conference, 2008

2007

Interactive presentation: Single-ended coding techniques for off-chip interconnects to commodity memory.

Mihir R. Choudhury, Kyle Ringgenberg, Scott Rixner, Kartik Mohanram

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Accurate and scalable reliability analysis of logic circuits.

Mihir R. Choudhury, Kartik Mohanram

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006

Design Optimization for Robustness to Single Event Upsets.

Quming Zhou, Mihir R. Choudhury, Kartik Mohanram

Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniques.

Mihir R. Choudhury, Quming Zhou, Kartik Mohanram

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

2005

Multiple Fault Testing of Logic Resources of SRAM-Based FPGAs.

Saurabh Goyal, Mihir R. Choudhury, S. S. S. P. Rao, L. Kalyan Kumar

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005