David S. Kung

Affiliations:
  • IBM Thomas J. Watson Research Center, Yorktown Heights, NY, USA
  • Stanford University, Department of Physics, CA, USA (PhD)


According to our database1, David S. Kung authored at least 33 papers between 1992 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2021
Asynchronous Decentralized Distributed Training of Acoustic Models.
IEEE ACM Trans. Audio Speech Lang. Process., 2021

Project CodeNet: A Large-Scale AI for Code Dataset for Learning a Diversity of Coding Tasks.
CoRR, 2021

CodeNet: A Large-Scale AI for Code Dataset for Learning a Diversity of Coding Tasks.
Proceedings of the Neural Information Processing Systems Track on Datasets and Benchmarks 1, 2021

NASTransfer: Analyzing Architecture Transferability in Large Scale Neural Architecture Search.
Proceedings of the Thirty-Fifth AAAI Conference on Artificial Intelligence, 2021

2020
Distributed Training of Deep Neural Network Acoustic Models for Automatic Speech Recognition: A comparison of current training strategies.
IEEE Signal Process. Mag., 2020

Large Scale Neural Architecture Search with Polyharmonic Splines.
CoRR, 2020

Distributed Training of Deep Neural Network Acoustic Models for Automatic Speech Recognition.
CoRR, 2020

Map Generation from Large Scale Incomplete and Inaccurate Data Labels.
Proceedings of the KDD '20: The 26th ACM SIGKDD Conference on Knowledge Discovery and Data Mining, 2020

Improving Efficiency in Large-Scale Decentralized Distributed Training.
Proceedings of the 2020 IEEE International Conference on Acoustics, 2020

2019
BlueConnect: Decomposing all-reduce for deep learning on heterogeneous network hierarchy.
IBM J. Res. Dev., 2019

BlueConnect: Decomposing All-Reduce for Deep Learning on Heterogeneous Network Hierarchy.
Proceedings of Machine Learning and Systems 2019, 2019

A Highly Efficient Distributed Deep Learning System for Automatic Speech Recognition.
Proceedings of the Interspeech 2019, 2019

Distributed Deep Learning Strategies for Automatic Speech Recognition.
Proceedings of the IEEE International Conference on Acoustics, 2019

2017
PowerAI DDL.
CoRR, 2017

DYCE: A Resilient Shared Memory Paradigm for Heterogenous Distributed Systems without Memory Coherence.
Proceedings of the Computing Frontiers Conference, 2017

2010
The Dawn of 22nm Era: Design and CAD Challenges.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

2009
Guest Editors' Introduction: Opportunities and Challenges of 3D Integration.
IEEE Des. Test Comput., 2009

The fate of stacking.
IEEE Des. Test Comput., 2009

CAD challenges for 3D ICs.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2005
Sensitivity guided net weighting for placement-driven synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Improving run times by pruned application of synthesis transforms.
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005

Minimizing power with flexible voltage islands.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
An Integrated Environment for Technology Closure of Deep-Submicron IC Designs.
IEEE Des. Test Comput., 2004

Timing closure for low-FO4 microprocessor design.
Proceedings of the 41th Design Automation Conference, 2004

2003
Pushing ASIC performance in a power envelope.
Proceedings of the 40th Design Automation Conference, 2003

2002
Fast and accurate wire delay estimation for physical synthesis of large ASICs.
Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002

2000
Combinatorial cell design for CMOS libraries.
Integr., 2000

1999
Optimal P/N width ratio selection for standard cell libraries.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

1998
Gate-size selection for standard cell libraries.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

A Fast Fanout Optimization Algorithm for Near-Continuous Buffer Libraries.
Proceedings of the 35th Conference on Design Automation, 1998

1996
BooleDozer: Logic synthesis for ASICs.
IBM J. Res. Dev., 1996

1992
Hazard-non-increasing gate-level optimization algorithms.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

BDDMAP: A Technology Mapper Based on a New Covering Algorithm.
Proceedings of the 29th Design Automation Conference, 1992


  Loading...