Sunwoo Kwon

According to our database1, Sunwoo Kwon authored at least 17 papers between 2004 and 2018.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2018
A 4.2-mW 10-MHz BW 74.4-dB SNDR Continuous-Time Delta-Sigma Modulator With SAR-Assisted Digital-Domain Noise Coupling.
IEEE J. Solid State Circuits, 2018

2012
A 0.018% THD+N, 88-dB PSRR PWM Class-D Amplifier for Direct Battery Hookup.
IEEE J. Solid State Circuits, 2012

A 0.028% THD+N, 91% power-efficiency, 3-level PWM Class-D amplifier with a true differential front-end.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2010
A 2.4ps resolution 2.1mW second-order noise-shaped time-to-digital converter with 3.2ns range in 1MHz bandwidth.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009
Comments on "Efficient Multibit Quantization in Continuous-Time Sigma Delta Modulators".
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

74 dB SNDR Multi-Loop Sturdy-MASH Delta-Sigma Modulator Using 35 dB Open-Loop Opamp Gain.
IEEE J. Solid State Circuits, 2009

A 630μW zero-crossing-based ΔΣ ADC using switched-resistor current sources in 45nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

An 11mW 100MHz 16X-OSR 64dB-SNDR hybrid CT/DT ΔΣ ADC with relaxed DEM timing.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

A continuous-time input pipeline ADC with inherent anti-alias filtering.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008
74dB SNDR multi-loop sturdy-MASH delta-sigma modulator using 35dB opamp gain.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
A Power-Efficient Two-Channel Time-Interleaved ΣΔ Modulator for Broadband Applications.
IEEE J. Solid State Circuits, 2007

Mixed-Order Sturdy MASH Delta-Sigma Modulator.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A High-Speed Delta-Sigma Modulator with Relaxed DEM Timing Requirement.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
A 5.4mW 2-Channel Time-Interleaved Multi-bit ΔΣ Modulator with 80dB SNR and 85dB DR for ADSL.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

A 14mW Multi-bit ΔΣ Modulator with 82dB SNR and 86dB DR for ADSL2+.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

A 1.2V, 3.5µW, 20MS/s, 8-bit comparator with dynamic-biasing preamplifier.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2004
Op-amp swing reduction in sigma-delta modulators.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004


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