Il-Hoon Jang

According to our database, Il-Hoon Jang authored at least 5 papers between 2015 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2022

A 4^th-Order Continuous-Time Delta-Sigma Modulator With Hybrid Noise-Coupling.

Kent Edrian Lozada, Il-Hoon Jang, Gyeom-Je Bae, Dong-Hun Lee, Ye-Dam Kim, Hankyu Lee, Seong Joong Kim, Seung-Tak Ryu

IEEE Trans. Circuits Syst. II Express Briefs, 2022

2021

A 12b 600MS/s Pipelined SAR and 2x-Interleaved Incremental Delta-Sigma ADC with Source-Follower-Based Residue-Transfer Scheme in 7nm FinFET.

Seung-Yeob Baek, Il-Hoon Jang, Michael Choi, Hyungdong Roh, Woongtaek Lim, Youngjae Cho, Jongshin Shin

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2018

A 4.2-mW 10-MHz BW 74.4-dB SNDR Continuous-Time Delta-Sigma Modulator With SAR-Assisted Digital-Domain Noise Coupling.

Il-Hoon Jang, Min-Jae Seo, Sang-Hyun Cho, Jae-Keun Lee, Seung-Yeob Baek, Sunwoo Kwon, Michael Choi, Hyung-Jong Ko, Seung-Tak Ryu

IEEE J. Solid State Circuits, 2018

2017

An incremental zoom sturdy MASH ADC.

Ki-Hoon Seo, Il-Hoon Jang, Kyung-Jun Noh, Seung-Tak Ryu

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

2015

26.4 A 21fJ/conv-step 9 ENOB 1.6GS/S 2× time-interleaved FATI SAR ADC with background offset and timing-skew calibration in 45nm CMOS.

Ba-Ro-Saim Sung, Dong-Shin Jo, Il-Hoon Jang, Dong-Suk Lee, Yong-Sang You, Yong-Hee Lee, Ho-Jin Park, Seung-Tak Ryu

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015