Shan Shen
Orcid: 0000-0003-1383-463X
According to our database1,
Shan Shen authored at least 34 papers
between 2005 and 2026.
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Bibliography
2026
Efficient Parallel ILU Factorization and Forward/Backward Substitution with Application to Large-Scale Nonlinear Circuit Simulation.
ACM Trans. Design Autom. Electr. Syst., May, 2026
Breaking the Tuning Barrier: Zero-Hyperparameters Yield Multi-Corner Analysis Via Learned Priors.
CoRR, March, 2026
CoRR, March, 2026
Integr., 2026
Proceedings of the Design, Automation & Test in Europe Conference, 2026
Effective RC Reduction via Graph Sparsification for Accurate Post-Simulation of Mixed-Signal ICs.
Proceedings of the 31st Asia and South Pacific Design Automation Conference, 2026
Proceedings of the 31st Asia and South Pacific Design Automation Conference, 2026
2025
Proceedings of the 43rd IEEE International Conference on Computer Design, 2025
Transferable Parasitic Estimation via Graph Contrastive Learning and Label Rebalancing in AMS Circuits.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2025
Few-shot Learning on AMS Circuits and Its Application to Parasitic Capacitance Prediction.
Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025
Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025
2024
Proceedings of the 25th International Symposium on Quality Electronic Design, 2024
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024
2023
A Timing Yield Model for SRAM Cells at Sub/Near-Threshold Voltages Based on a Compact Drain Current Model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2023
IEEE Trans. Circuits Syst. II Express Briefs, March, 2023
Parallel Incomplete LU Factorization Based Iterative Solver for Fixed-Structure Linear Equations in Circuit Simulation.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
2022
A Timing Yield Model for SRAM Cells in Sub/Near-threshold Voltages Based on A Compact Drain Current Model.
CoRR, 2022
2021
A Design of Timing Speculation SRAM-Based L1 Caches With PVT Autotracking Under Near-Threshold Voltages.
IEEE Trans. Very Large Scale Integr. Syst., 2021
A Spline-High Dimensional Model Representation for SRAM Yield Estimation in High Sigma and High Dimensional Scenarios.
IEEE Access, 2021
2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
2019
Lowering the Hit Latencies of Low Voltage Caches Based on the Cross-Sensing Timing Speculation SRAM.
IEEE Access, 2019
RRS cache: a low voltage cache based on timing speculation SRAM with a reuse-aware cacheline remapping mechanism.
Proceedings of the International Symposium on Memory Systems, 2019
2018
J. Syst. Archit., 2018
2012
Cortical activation during executed, imagined, observed, and passive wrist movements in healthy volunteers and stroke patients.
NeuroImage, 2012
2009
Evaluation of the effective connectivity of supplementary motor areas during motor imagery using Granger causality mapping.
NeuroImage, 2009
The functional magnetic resonance imaging (fMRI) procedure as experienced by healthy participants and stroke patients - A pilot study.
BMC Medical Imaging, 2009
2008
Detection of Infarct Lesions From Single MRI Modality Using Inconsistency Between Voxel Intensity and Spatial Location - A 3-D Automatic Approach.
IEEE Trans. Inf. Technol. Biomed., 2008
2007
2006
Proceedings of the 28th International Conference of the IEEE Engineering in Medicine and Biology Society, 2006
2005
MRI fuzzy segmentation of brain tissue using neighborhood attraction with neural-network optimization.
IEEE Trans. Inf. Technol. Biomed., 2005