Mozhgan Mansuri

Orcid: 0000-0002-0277-7775

According to our database¹, Mozhgan Mansuri authored at least 27 papers between 2002 and 2024.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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In proceedings

Article

PhD thesis

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On csauthors.net:

Bibliography

2024

18.2 A 4x64Gb/s NRZ 1.3pJ/b Co-Packaged and Fiber-Terminated 4-Ch VCSEL-Based Optical Transmitter.

[BibT_eX]

[DOI]

Susnata Mondal

Junyi Qiu

Sashank Krishnamurthy

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2022

A Scalable 32-56 Gb/s 0.56-1.28 pJ/b Voltage-Mode VCSEL-Based Optical Transmitter in 28-nm CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2022

2021

A Scalable 32-to-56Gb/s 0.56-to-1.28pJ/b Voltage-Mode VCSEL-Based Optical Transmitter in 28nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

2018

A Digital-Intensive 2-to-9.2 GB/S/Pin Memory Controller I/O with Fast-Response LDO in 10NM CMOS.

[BibT_eX]

[DOI]

Rajesh Inti

Mozhgan Mansuri

Joe Kennedy

Hariprasath Venkatram

Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

2015

An On-Die All-Digital Power Supply Noise Analyzer With Enhanced Spectrum Measurements.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2015

2014

A 4-32 Gb/s Bidirectional Link With 3-Tap FFE/6-Tap DFE and Collaborative CDR in 22 nm CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2014

26.2 A 205mW 32Gb/s 3-Tap FFE/6-tap DFE bidirectional serial link in 22nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

26.4 A 25.6Gb/s differential and DDR4/GDDR5 dual-mode transmitter with digital clock calibration in 22nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013

A Scalable 0.128-1 Tb/s, 0.8-2.6 pJ/bit, 64-Lane Parallel I/O in 32-nm CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2013

A scalable 0.128-to-1Tb/s 0.8-to-2.6pJ/b 64-lane parallel I/O in 32nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

Design considerations for low-power receiver front-end in high-speed data links.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012

An on-die all-digital delay measurement circuit with 250fs accuracy.

[BibT_eX]

[DOI]

Mozhgan Mansuri

Bryan Casper

Frank O'Mahony

Proceedings of the Symposium on VLSI Circuits, 2012

2010

A 47 , ˟, 10 Gb/s 1.4 mW/Gb/s Parallel Interface in 45 nm CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2010

A 47×10Gb/s 1.4mW/(Gb/s) parallel interface in 45nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A 5-to-25Gb/s 1.6-to-3.8mW/(Gb/s) reconfigurable transceiver in 45nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009

Strong Injection Locking in Low- Q LC Oscillators: Modeling and Application in a Forwarded-Clock I/O Receiver.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2009

2008

A Scalable 5-15 Gbps, 14-75 mW Low-Power I/O Transceiver in 65 nm CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2008

A 27Gb/s Forwarded-Clock I/O Receiver Using an Injection-Locked LC-DCO in 45nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

Strong injection locking of low-Q LC oscillators.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007

Future Microprocessor Interfaces: Analysis, Design and Optimization.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006

A 20Gb/s Embedded Clock Transceiver in 90nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

A 20Gb/s Forwarded Clock Transceiver in 90nm CMOS B.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2004

A 27-mW 3.6-gb/s I/O transceiver.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2004

2003

Methodology for on-chip adaptive jitter minimization in phase-locked loops.

[BibT_eX]

[DOI]

Mozhgan Mansuri

A. Hadiashar

Chih-Kong Ken Yang

IEEE Trans. Circuits Syst. II Express Briefs, 2003

A low-power adaptive bandwidth PLL and clock buffer with supply-noise compensation.

[BibT_eX]

[DOI]

Mozhgan Mansuri

Chih-Kong Ken Yang

IEEE J. Solid State Circuits, 2003

2002

Fast frequency acquisition phase-frequency detectors for Gsamples/s phase-locked loops.

[BibT_eX]

[DOI]

Mozhgan Mansuri

Dean Liu

Chih-Kong Ken Yang

IEEE J. Solid State Circuits, 2002

Jitter optimization based on phase-locked loop design parameters.

[BibT_eX]

[DOI]

Mozhgan Mansuri

Chih-Kong Ken Yang

IEEE J. Solid State Circuits, 2002

Mozhgan Mansuri

Timeline

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