James E. Jaussi

According to our database1, James E. Jaussi authored at least 23 papers between 2007 and 2019.

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Bibliography

2019
A 42.2Gb/s 4.3pJ/b 60GHz Digital Transmitter with 12b/Symbol Polarization MIMO.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2018
A 60-GHz Transceiver and Baseband With Polarization MIMO in 28-nm CMOS.
J. Solid-State Circuits, 2018

A Digital-Intensive 2-to-9.2 GB/S/Pin Memory Controller I/O with Fast-Response LDO in 10NM CMOS.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

A 40Gb/s 6pJ/b RX baseband in 28nm CMOS for 60GHz polarization MIMO.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

A 27.8Gb/s 11.5pJ/b 60GHz transceiver in 28nm CMOS with polarization MIMO.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

A 112 Gb/s PAM4 Linear TIA with 0.96 pJ/bit Energy Efficiency in 28 nm CMOS.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

High-speed contactless I/O for computing devices.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

2017
A 25 Gb/s 60 GHz digital power amplifier in 28nm CMOS.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

2016
A 32 Gb/s Bidirectional 4-channel 4 pJ/b Capacitively Coupled Link in 14 nm CMOS for Proximity Communication.
J. Solid-State Circuits, 2016

23.2 A 32Gb/s bidirectional 4-channel 4pJ/b capacitively coupled link in 14nm CMOS for proximity communication.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015
A 1.2-5Gb/s 1.4-2pJ/b serial link in 22nm CMOS with a direct data-sequencing blind oversampling CDR.
Proceedings of the Symposium on VLSI Circuits, 2015

A 0.5-to-0.75V, 3-to-8 Gbps/lane, 385-to-790 fJ/b, bi-directional, quad-lane forwarded-clock transceiver in 22nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2015

2014
A 4-32 Gb/s Bidirectional Link With 3-Tap FFE/6-Tap DFE and Collaborative CDR in 22 nm CMOS.
J. Solid-State Circuits, 2014

2013
A Scalable 0.128-1 Tb/s, 0.8-2.6 pJ/bit, 64-Lane Parallel I/O in 32-nm CMOS.
J. Solid-State Circuits, 2013

A scalable 0.128-to-1Tb/s 0.8-to-2.6pJ/b 64-lane parallel I/O in 32nm CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

Design considerations for low-power receiver front-end in high-speed data links.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2010
A 47 , ˟, 10 Gb/s 1.4 mW/Gb/s Parallel Interface in 45 nm CMOS.
J. Solid-State Circuits, 2010

A 47×10Gb/s 1.4mW/(Gb/s) parallel interface in 45nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A 5-to-25Gb/s 1.6-to-3.8mW/(Gb/s) reconfigurable transceiver in 45nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009
Strong Injection Locking in Low- Q LC Oscillators: Modeling and Application in a Forwarded-Clock I/O Receiver.
IEEE Trans. on Circuits and Systems, 2009

2008
A 27Gb/s Forwarded-Clock I/O Receiver Using an Injection-Locked LC-DCO in 45nm CMOS.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

Strong injection locking of low-Q LC oscillators.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
Future Microprocessor Interfaces: Analysis, Design and Optimization.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007


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