Tawfiq Musah

Orcid: 0000-0002-6703-9490

According to our database1, Tawfiq Musah authored at least 19 papers between 2009 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Online presence:

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Bibliography

2024
Jitter-Based Authentication for Automotive Wireline Networks.
IEEE Access, 2024

2023
A digitally controlled switched-ring oscillator-based time domain multiply-and-accumulate core for machine learning.
Int. J. Circuit Theory Appl., October, 2023

Hybrid Timing Error Detector for Baud Rate Multilevel Clock and Data Recovery.
IEEE Open J. Circuits Syst., 2023

Complexity reduction in multilevel speculative DFEs with unconstrained receiver response.
Microelectron. J., 2023

Time-Based Optical Receiver Featuring a Linear Current-to-Time Conversion with Equalization.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

2022
Robust Timing Error Detection for Multilevel Baud-Rate CDR.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Characterization of Sub-Nyquist TIA with Equalization in Optical Receivers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021
Hysteretic Error Extraction in Multi-Level Wireline Receivers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

The Effect of Equalization on Nonlinearity in Time-Based Decision Feedback Equalizers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
Time-Based Error Extraction for Multilevel Receivers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2014
A 4-32 Gb/s Bidirectional Link With 3-Tap FFE/6-Tap DFE and Collaborative CDR in 22 nm CMOS.
IEEE J. Solid State Circuits, 2014

26.2 A 205mW 32Gb/s 3-Tap FFE/6-tap DFE bidirectional serial link in 22nm CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

26.4 A 25.6Gb/s differential and DDR4/GDDR5 dual-mode transmitter with digital clock calibration in 22nm CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2012
The effect of correlated level shifting on noise performance in switched capacitor circuits.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
A 30% beyond VDD signal swing 9-ENOB pipelined ADC using a 1.2V 30dB loop-gain opamp.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2010
Design of a 79 dB 80 MHz 8X-OSR Hybrid Delta-Sigma/Pipelined ADC.
IEEE J. Solid State Circuits, 2010

An interstage correlated double sampling technique for switched-capacitor gain stages.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Pseudo-differential zero-crossing-based circuit with differential error suppression.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
A 630μW zero-crossing-based ΔΣ ADC using switched-resistor current sources in 45nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009


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