Timothy O. Dickson
Orcid: 0000-0002-0361-031X
According to our database1,
Timothy O. Dickson
authored at least 30 papers
between 2002 and 2023.
Collaborative distances:
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Bibliography
2023
A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links.
IEEE J. Solid State Circuits, 2023
2022
An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
A 72GS/s, 8-bit DAC-based Wireline Transmitter in 4nm FinFET CMOS for 200+Gb/s Serial Links.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
2020
Errata Erratum to "A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS".
IEEE J. Solid State Circuits, 2020
IEEE J. Solid State Circuits, 2020
2019
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2019
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2018
IEEE J. Solid State Circuits, 2018
2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2016
A 1.8 pJ/bit 16×16Gb/s Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration.
IEEE J. Solid State Circuits, 2016
2015
A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology.
IEEE J. Solid State Circuits, 2015
A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
2014
A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
2012
An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects.
IEEE J. Solid State Circuits, 2012
A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOS.
IEEE J. Solid State Circuits, 2012
A 19Gb/s serial link receiver with both 4-tap FFE and 5-tap DFE functions in 45nm SOI CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
2009
IEEE J. Solid State Circuits, 2009
A 12-Gb/s 11-mW Half-Rate Sampled 5-Tap Decision Feedback Equalizer With Current-Integrating Summers in 45-nm SOI CMOS Technology.
IEEE J. Solid State Circuits, 2009
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
A 78mW 11.1Gb/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
2007
Low-Power Circuits for a 2.5-V, 10.7-to-86-Gb/s Serial Transmitter in 130-nm SiGe BiCMOS.
IEEE J. Solid State Circuits, 2007
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
2006
The Invariance of Characteristic Current Densities in Nanoscale MOSFETs and Its Impact on Algorithmic Design Methodologies and Design Porting of Si(Ge) (Bi)CMOS High-Speed Building Blocks.
IEEE J. Solid State Circuits, 2006
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006
2005
An 80-Gb/s 2<sup>31</sup>-1 pseudorandom binary sequence generator in SiGe BiCMOS technology.
IEEE J. Solid State Circuits, 2005
IEEE J. Solid State Circuits, 2005
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005
Algorithmic design methodologies and design porting of wireline transceiver IC building blocks between technology nodes.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005
2004
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004
2002
Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 2002