Naina Gupta

Orcid: 0000-0003-3056-9241

Affiliations:
  • Fraunhofer Singapore, Singapore
  • Indraprashtha Institute of Information Technology, (IIIT-Delhi), India (former)


According to our database1, Naina Gupta authored at least 17 papers between 2016 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2024
A Configurable CRYSTALS-Kyber Hardware Implementation with Side-Channel Protection.
ACM Trans. Embed. Comput. Syst., March, 2024

EFFLUX-F2: A High Performance Hardware Security Evaluation Board.
IACR Cryptol. ePrint Arch., 2024

2023
SoCFaSe: in quest for fast and secure SoC architectures
PhD thesis, 2023

Lightweight Hardware Accelerator for Post-Quantum Digital Signature CRYSTALS-Dilithium.
IEEE Trans. Circuits Syst. I Regul. Pap., 2023

AI Attacks AI: Recovering Neural Network architecture from NVDLA using AI-assisted Side Channel Attack.
IACR Cryptol. ePrint Arch., 2023

BAKSHEESH: Similar Yet Different From GIFT.
IACR Cryptol. ePrint Arch., 2023

CRYSTALS-Dilithium on RISC-V Processor: Lightweight Secure Boot Using Post-Quantum Digital Signature.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

2021
PQC Acceleration Using GPUs: FrodoKEM, NewHope, and Kyber.
IEEE Trans. Parallel Distributed Syst., 2021

MemEnc: A Lightweight, Low-Power, and Transparent Memory Encryption Engine for IoT.
IEEE Internet Things J., 2021

In Quest for Fast and Secure SoC.
Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021

2020
Threshold Implementations of <tt>GIFT</tt>: A Trade-Off Analysis.
IEEE Trans. Inf. Forensics Secur., 2020

Towards Designing a Secure RISC-V System-on-Chip: ITUS.
J. Hardw. Syst. Secur., 2020

Post-Quantum Secure Boot.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
SPQCop: Side-channel protected Post-Quantum Cryptoprocessor.
IACR Cryptol. ePrint Arch., 2019

XMSS and Embedded Systems.
Proceedings of the Selected Areas in Cryptography - SAC 2019, 2019

2018
XMSS and Embedded Systems - XMSS Hardware Accelerators for RISC-V.
IACR Cryptol. ePrint Arch., 2018

2016
Exploiting the Leakage: Analysis of Some Authenticated Encryption Schemes.
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2016


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