Nak Hee Seong

According to our database1, Nak Hee Seong authored at least 9 papers between 2006 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2020
2.4 A 7nm High-Performance and Energy-Efficient Mobile Application Processor with Tri-Cluster CPUs and a Sparsity-Aware NPU.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2013
Pragmatic Integration of an SRAM Row Cache in Heterogeneous 3-D DRAM Architecture Using TSV.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Tri-level-cell phase change memory: toward an efficient and reliable memory system.
Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

2012
A reliable, secure phase-change memory as a main memory.
PhD thesis, 2012

2011
Security Refresh: Protecting Phase-Change Memory against Malicious Wear Out.
IEEE Micro, 2011

2010
SAFER: Stuck-At-Fault Error Recovery for Memories.
Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010

Security refresh: prevent malicious wear-out and increase durability for phase-change memory with dynamically randomized address mapping.
Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010

An optimized 3D-stacked memory architecture by exploiting excessive, high-density TSV bandwidth.
Proceedings of the 16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), 2010

2006
An SoC with 1.3 gtexels/s 3-D graphics full pipeline for consumer applications.
IEEE J. Solid State Circuits, 2006


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