Narasinga Rao Miniskar

Orcid: 0000-0001-8259-8891

According to our database1, Narasinga Rao Miniskar authored at least 29 papers between 2009 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Abisko: Deep codesign of an architecture for spiking neural networks using novel neuromorphic materials.
Int. J. High Perform. Comput. Appl., July, 2023

MatRIS: Multi-level Math Library Abstraction for Heterogeneity and Performance Portability using IRIS Runtime.
Proceedings of the SC '23 Workshops of The International Conference on High Performance Computing, 2023

Tiling Framework for Heterogeneous Computing of Matrix based Tiled Algorithms.
Proceedings of the 2nd International Workshop on Extreme Heterogeneity Solutions, 2023

A 3D Implementation of Convolutional Neural Network for Fast Inference.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

An FPGA-Based Neuromorphic Processor with All-to-All Connectivity.
Proceedings of the IEEE International Conference on Rebooting Computing, 2023

On-Sensor Data Filtering using Neuromorphic Computing for High Energy Physics Experiments.
Proceedings of the 2023 International Conference on Neuromorphic Systems, 2023

IRIS-DMEM: Efficient Memory Management for Heterogeneous Computing.
Proceedings of the IEEE High Performance Extreme Computing Conference, 2023

2022
Adrastea: An Efficient FPGA Design Environment for Heterogeneous Scientific Computing and Machine Learning.
Proceedings of the Accelerating Science and Engineering Discoveries Through Integrated Research Infrastructure for Experiment, Big Data, Modeling and Simulation, 2022

LaRIS: Targeting Portability and Productivity for LAPACK Codes on Extreme Heterogeneous Systems by Using IRIS.
Proceedings of the IEEE/ACM Redefining Scalability for Diversely Heterogeneous Architectures Workshop, 2022

IRIS-BLAS: Towards a Performance Portable and Heterogeneous BLAS Library.
Proceedings of the 29th IEEE International Conference on High Performance Computing, 2022

Ultra Low Latency Machine Learning for Scientific Edge Applications.
Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

2021
A Hierarchical Task Scheduler for Heterogeneous Computing.
Proceedings of the High Performance Computing - 36th International Conference, 2021

A Memory Efficient Lock-Free Circular Queue.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Toward Performance Portable Programming for Heterogeneous Systems on a Chip: A Case Study with Qualcomm Snapdragon SoC.
Proceedings of the 2021 IEEE High Performance Extreme Computing Conference, 2021

2020
Deffe: a data-efficient framework for performance characterization in domain-specific computing.
Proceedings of the 17th ACM International Conference on Computing Frontiers, 2020

2019
Low Complex & High Accuracy Computation Approximations to Enable On-Device RNN Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
Optimal SDRAM Buffer Allocator for Efficient Reuse of Layer IO in CNNs Inference Framework.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Accurate and Efficient Fixed Point Inference for Deep Neural Networks.
Proceedings of the 2018 IEEE International Conference on Image Processing, 2018

An Intelligent Bandwidth Manager for CNN Applications on Embedded Devices.
Proceedings of the 2018 IEEE International Conference on Image Processing, 2018

2017
Fast cycle-accurate compile based simulator for reconfigurable processor.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A novel method to regenerate an optimal CNN by exploiting redundancy patterns in the network.
Proceedings of the 2017 IEEE International Conference on Image Processing, 2017

2016
Intra mode power saving methodology for CGRA-based reconfigurable processor architectures.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2014
Retargetable automatic generation of compound instructions for CGRA based reconfigurable processor applications.
Proceedings of the 2014 International Conference on Compilers, 2014

2012
System Scenario Based Resource Management of Processing Elements on MPSoC (Systeemscenario-gebaseerd beheer van taken op multiprocessor systemen-op-chip (MPSoC)).
PhD thesis, 2012

Memory and communication driven spatio-temporal scheduling on MPSoCs.
Proceedings of the 25th Symposium on Integrated Circuits and Systems Design, 2012

Function inlining and loop unrolling for loop acceleration in reconfigurable processors.
Proceedings of the 15th International Conference on Compilers, 2012

2011
SAMOSA: Scratchpad aware mapping of streaming applications.
Proceedings of the 2011 International Symposium on System on Chip, 2011

2010
PinComm: Characterizing Intra-application Communication for the Many-Core Era.
Proceedings of the 16th IEEE International Conference on Parallel and Distributed Systems, 2010

2009
Scenario Based Mapping of Dynamic Applications on MPSoC: A 3D Graphics Case Study.
Proceedings of the Embedded Computer Systems: Architectures, 2009


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