Georgios Ioannis Paliaroutis

According to our database1, Georgios Ioannis Paliaroutis authored at least 7 papers between 2016 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2023
Accurate Soft Error Rate Evaluation Using Event-Driven Dynamic Timing Analysis.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023

2021
On the Impact of Electrical Masking and Timing Analysis on Soft Error Rate Estimation in Deep Submicron Technologies.
Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021

2020
A Layout-Based Soft Error Rate Estimation and Mitigation in the Presence of Multiple Transient Faults in Combinational Logic.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

2019
Multiple Transient Faults in Combinational Logic with Placement Considerations.
Proceedings of the 8th International Conference on Modern Circuits and Systems Technologies, 2019

2018
A Placement-Aware Soft Error Rate Estimation of Combinational Circuits for Multiple Transient Faults in CMOS Technology.
Proceedings of the 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2018

2017
Placement-based SER estimation in the presence of multiple faults in combinational logic.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

2016
SER Analysis of Multiple Transient Faults in Combinational Logic.
Proceedings of the SouthEast European Design Automation, 2016


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