Vidya A. Chhabria

Orcid: 0000-0002-3273-0724

According to our database1, Vidya A. Chhabria authored at least 25 papers between 2019 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
A Machine Learning Approach to Improving Timing Consistency between Global Route and Detailed Route.
ACM Trans. Design Autom. Electr. Syst., January, 2024

IR-Aware ECO Timing Optimization Using Reinforcement Learning.
CoRR, 2024

ECO-CHIP: Estimation of Carbon Footprint of Chiplet-based Architectures for Sustainable VLSI.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024

2023
Encoder-Decoder Networks for Analyzing Thermal and Power Delivery Networks.
ACM Trans. Design Autom. Electr. Syst., January, 2023

GreenFPGA: Evaluating FPGAs as Environmentally Sustainable Computing Solutions.
CoRR, 2023

Towards Sustainable Computing: Assessing the Carbon Footprint of Heterogeneous Systems.
CoRR, 2023

Analysis of Pattern-dependent Rapid Thermal Annealing Effects on SRAM Design.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

Recent Progress in the Analysis of Electromigration and Stress Migration in Large Multisegment Interconnects.
Proceedings of the 2023 International Symposium on Physical Design, 2023

Frequency-Domain Transient Electromigration Analysis Using Circuit Theory.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Invited Paper: CircuitOps: An ML Infrastructure Enabling Generative AI for VLSI Circuit Optimization.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Invited Paper: 2023 ICCAD CAD Contest Problem C: Static IR Drop Estimation Using Machine Learning.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Benchmarking Heterogeneous Integration with 2.5D/3D Interconnect Modeling.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

2022
OpeNPDN: A Neural-Network-Based Framework for Power Delivery Network Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

XT-PRAGGMA: Crosstalk Pessimism Reduction Achieved with GPU Gate-level Simulations and Machine Learning.
Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD, 2022

From Global Route to Detailed Route: ML for Fast and Accurate Wire Parasitics and Timing Prediction.
Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD, 2022

2021
A Linear-Time Algorithm for Steady-State Analysis of Electromigration in General Interconnects.
CoRR, 2021

Analytical Modeling of Transient Electromigration Stress based on Boundary Reflections.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

BeGAN: Power Grid Benchmark Generation Using a Process-portable GAN-based Methodology.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

MAVIREC: ML-Aided Vectored IR-Drop Estimation and Classification.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

A New, Computationally Efficient "Blech Criterion" for Immortality in General Interconnects.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Thermal and IR Drop Analysis Using Convolutional Encoder-Decoder Networks.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020
MAVIREC: ML-Aided Vectored IR-DropEstimation and Classification.
CoRR, 2020

Template-based PDN Synthesis in Floorplan and Placement Using Classifier and CNN Techniques.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019
Impact of Self-heating on Performance and Reliability in FinFET and GAAFET Designs.
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

Toward an Open-Source Digital Flow: First Learnings from the OpenROAD Project.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019


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