Netanel Shavit

Orcid: 0000-0003-2011-6329

According to our database1, Netanel Shavit authored at least 9 papers between 2020 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
Revisiting Dynamic Logic - A True Candidate for Energy-Efficient Cryogenic Operation in Nanoscaled Technologies.
IEEE Trans. Circuits Syst. I Regul. Pap., March, 2024

2023
Programmable All-in-One 4×8-/2×16-/1×32-Bits Dual Mode Logic Multiplier in 16 nm FinFET With Semi-Automatic Flow.
IEEE Access, 2023

2022
A Method for Mitigation of Droop Timing Errors Including a 500 MHz Droop Detector and Dual Mode Logic.
IEEE J. Solid State Circuits, 2022

2021
Live Demo: Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Live Demonstration: A 0.8V, 1.54 pJ / 940 MHz Dual Mode Logic-Based 16x16-Bit Booth Multiplier in 16-nm FinFET.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

Dual Mode Logic Address Decoder.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Exploiting Single-Well Design for Energy-Efficient Ultra-Wide Voltage Range Dual Mode Logic-Based Digital Circuits in 28nm FD-SOI Technology.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Robust Dual Mode Pass Logic (DMPL) for Energy Efficiency and High Performance.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020


  Loading...