Alexander Fish

Orcid: 0000-0002-4994-1536

According to our database1, Alexander Fish authored at least 110 papers between 2001 and 2024.

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Bibliography

2024
Guest Editorial Special Issue on the IEEE Latin American Symposium on Circuits and Systems (LASCAS 2023).
IEEE Trans. Circuits Syst. I Regul. Pap., March, 2024

Revisiting Dynamic Logic - A True Candidate for Energy-Efficient Cryogenic Operation in Nanoscaled Technologies.
IEEE Trans. Circuits Syst. I Regul. Pap., March, 2024

2023
On-chip fully reconfigurable Artificial Neural Network in 16 nm FinFET for Positron Emission Tomography.
CoRR, 2023

Silicon Proven 1.29 μm × 1.8 μm 65nm Sub-Vt Optical Sensor for Hardware Security Applications.
IEEE Access, 2023

Programmable All-in-One 4×8-/2×16-/1×32-Bits Dual Mode Logic Multiplier in 16 nm FinFET With Semi-Automatic Flow.
IEEE Access, 2023

Toward a Monolithic Pixel Sensor for Heavy Ion Spectroscopy - Pixel Structure Design and Optimization.
IEEE Access, 2023

Overview of Cryogenic Operation in Nanoscale Technology Nodes.
Proceedings of the 14th IEEE Latin America Symposium on Circuits and System, 2023

2022
A Method for Mitigation of Droop Timing Errors Including a 500 MHz Droop Detector and Dual Mode Logic.
IEEE J. Solid State Circuits, 2022

Evaluation of Dual Mode Logic Under Cryogenic Temperatures.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Mirror<sup>N</sup> PUF: Harvesting Multiple Independent Bits From Each PUF Cell in 65nm.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021
Low-Cost Side-Channel Secure Standard 6T-SRAM-Based Memory With a 1% Area and Less Than 5% Latency and Power Overheads.
IEEE Access, 2021

Live Demo: Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Live Demonstration: A 0.8V, 1.54 pJ / 940 MHz Dual Mode Logic-Based 16x16-Bit Booth Multiplier in 16-nm FinFET.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

Temporal Power Redistribution as a Countermeasure against Side-Channel Attacks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Dual Mode Logic Address Decoder.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Exploiting Single-Well Design for Energy-Efficient Ultra-Wide Voltage Range Dual Mode Logic-Based Digital Circuits in 28nm FD-SOI Technology.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Robust Dual Mode Pass Logic (DMPL) for Energy Efficiency and High Performance.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Weight Based Current Assisted Photonic Demodulator (WBCAPD) - Expansion towards Neuromorphic Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
Silicon Proven 1.8 µm × 9.2 µm 65-nm Digital Bit Generator for Hardware Security Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

A 7T Security Oriented SRAM Bitcell.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

An 88-fJ/40-MHz [0.4 V]-0.61-pJ/1-GHz [0.9 V] Dual-Mode Logic 8 × 8 bit Multiplier Accumulator With a Self-Adjustment Mechanism in 28-nm FD-SOI.
IEEE J. Solid State Circuits, 2019

Compact Sub-Vt Optical Sensor for the Detection of Fault Injection in Hardware Security Applications.
Proceedings of the 10th IFIP International Conference on New Technologies, 2019

FPGA Implementation of pAsynch Design Paradigm.
Proceedings of the 10th IFIP International Conference on New Technologies, 2019

Live Demo: An 88fJ / 40 MHz [0.4V] - 0.61pJ / 1GHz [0.9V] Dual Mode Logic 8×8-Bit Multiplier Accumulator with a Self-Adjustment Mechanism in 28 nm FD-SOI.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

An SRAM PUF with 2 Independent Bits/Cell in 65nm.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Power Analysis Resilient SRAM Design Implemented with a 1% Area Overhead Impedance Randomization Unit for Security Applications.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

2018
Low-Cost Pseudoasynchronous Circuit Design Style With Reduced Exploitable Side Information.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Leakage Power Attack-Resilient Symmetrical 8T SRAM Cell.
IEEE Trans. Very Large Scale Integr. Syst., 2018

A Low Noise Low Offset Readout Circuit for Magnetic-Random-Access-Memory.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A 4-Transistor nMOS-Only Logic-Compatible Gain-Cell Embedded DRAM With Over 1.6-ms Retention Time at 700 mV in 28-nm FD-SOI.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

An 800-MHz Mixed- V<sub>T</sub> 4T IFGC Embedded DRAM in 28-nm CMOS Bulk Process for Approximate Storage Applications.
IEEE J. Solid State Circuits, 2018

Delocalisation of one-dimensional marginals of product measures and the capacity of LTI discrete channels.
CoRR, 2018

Live Demonstration: An 800 Mhz Gain-Cell Embedded DRAM in 28 nm CMOS Bulk Process for Approximate Computing Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Embedded randomness and data dependencies design paradigm: Advantages and challenges.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Utilization of Process and Supply Voltage Random Variations for Random Bit Generation.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017
CPA Secured Data-Dependent Delay-Assignment Methodology.
IEEE Trans. Very Large Scale Integr. Syst., 2017

A 0.65-V, 500-MHz Integrated Dynamic and Static RAM for Error Tolerant Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2017

A Survey of the Sensitivities of Security Oriented Flip-Flop Circuits.
IEEE Access, 2017


Evaluation of Dual Mode Logic in 28nm FD-SOI technology.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Vulnerability of secured IoT memory against localized back side laser fault injection.
Proceedings of the Seventh International Conference on Emerging Security Technologies, 2017

An 800 Mhz mixed-VT 4T gain-cell embedded DRAM in 28 nm CMOS bulk process for approximate computing applications.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

2016
Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2016

A Low-Voltage Radiation-Hardened 13T SRAM Bitcell for Ultralow Power Space Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Silicon-Proven, Per-Cell Retention Time Distribution Model for Gain-Cell Based eDRAMs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

CMOS Based Gates for Blurring Power Information.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

Synthesis of Dual Mode Logic.
Integr., 2016

Extended exploration of low granularity back biasing control in 28nm UTBB FD-SOI technology.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A process compensated gain cell embedded-DRAM for ultra-low-power variation-aware design.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
Randomized Multitopology Logic Against Differential Power Analysis.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Data-Dependent Delays as a Barrier Against Power Attacks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

DPA-Secured Quasi-Adiabatic Logic (SQAL) for Low-Power Passive RFID Tags Employing S-Boxes.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Design Flow and Characterization Methodology for Dual Mode Logic.
IEEE Access, 2015

2014
Logical Effort for CMOS-Based Dual Mode Logic Gates.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Replica Technique for Adaptive Refresh Timing of Gain-Cell-Embedded DRAM.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

A Low Energy and High Performance ${\rm DM}^{2}$ Adder.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

A Low-Power Low-Cost 24 GHz RFID Tag With a C-Flash Based Embedded Memory.
IEEE J. Solid State Circuits, 2014

Full-Swing Gate Diffusion Input logic - Case-study of low-power CLA adder design.
Integr., 2014

Performance estimates of the pseudo-random method for radar detection.
Proceedings of the 2014 IEEE International Symposium on Information Theory, Honolulu, HI, USA, June 29, 2014

4T Gain-Cell with internal-feedback for ultra-low retention power at scaled CMOS nodes.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Secured Dual Mode Logic (DML) as a countermeasure against Differential Power Analysis.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013
Efficiency Optimization of a Step-Down Switched Capacitor Converter for Subthreshold.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Subthreshold Dual Mode Logic.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Delay-Doppler Channel Estimation in Almost Linear Complexity.
IEEE Trans. Inf. Theory, 2013

Hardware Implementation of a Digital Watermarking System for Video Authentication.
IEEE Trans. Circuits Syst. Video Technol., 2013

Functionality and stability analysis of a 400 mV quasi-static RAM (QSRAM) bitcell.
Microelectron. J., 2013

Low voltage dual mode logic: Model analysis and parameter extraction.
Microelectron. J., 2013

A Low-Power DCVSL-Like GIDL-Free Voltage Driver for Low-Cost RFID Nonvolatile Memory.
IEEE J. Solid State Circuits, 2013

Almost Linear Complexity Methods for Delay-Doppler Channel Estimation.
CoRR, 2013

Dual Mode Logic - Design for Energy Efficiency and High Performance.
IEEE Access, 2013

The Incidence and Cross methods for efficient radar detection.
Proceedings of the 51st Annual Allerton Conference on Communication, 2013

2012
A 40-nm Sub-Threshold 5T SRAM Bit Cell With Improved Read and Write Stability.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

Low-Voltage 96 dB Snapshot CMOS Image Sensor with 4.5 nW Power Dissipation per Pixel.
Sensors, 2012

Delay-Doppler channel estimation with almost linear complexity: To Solomon Golomb for the occasion of his 80 birthday mazel tov.
Proceedings of the 2012 IEEE International Symposium on Information Theory, 2012

State space modeling for sub-threshold SRAM stability analysis.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

High speed Dual Mode Logic Carry Look Ahead Adder.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A low-cost low-power non-volatile memory for RFID applications.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A GIDL free tunneling gate driver for a low power non-volatile memory array.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
A Wide-Dynamic-Range CMOS Image Sensor With Gating for Night Vision Systems.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

A 250 mV 8 kb 40 nm Ultra-Low Power 9T Supply Feedback SRAM (SF-SRAM).
IEEE J. Solid State Circuits, 2011

Computing the Matched Filter in Linear Time
CoRR, 2011

Low voltage SRAMs and the scalability of the 9T Supply Feedback SRAM.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

An improved model for delay/energy estimation in near-threshold flip-flops.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2009
Ultra-low Power Subthreshold Flip-flop Design.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008
A Low-Light CMOS Contact Imager With an Emission Filter for Biosensing Applications.
IEEE Trans. Biomed. Circuits Syst., 2008

Autonomous CMOS image sensor for real time target detection and tracking.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Low-power "Smart" CMOS image sensors.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A Low noise CMOS image sensor with an emission filter for fluorescence applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Hardware implementation of a DCT watermark for CMOS image sensors.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

A simplified approach for designing secure Random Number Generators in HW.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2007
Global Shutter CMOS Image Sensor With Wide Dynamic Range.
IEEE Trans. Circuits Syst. II Express Briefs, 2007

Low Power CMOS Image Sensors Employing Adaptive Bulk Biasing Control (AB2C) Approach.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
CMOS Image Sensors With Self-Powered Generation Capability.
IEEE Trans. Circuits Syst. II Express Briefs, 2006

Global Shutter CMOS Image Sensor With Wide Dynamic Range.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

2005
High-speed and high-precision current winner-take-all circuit.
IEEE Trans. Circuits Syst. II Express Briefs, 2005

Wide dynamic range snapshot APS for ultra low-power applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2005

Self-powered active pixel sensors for ultra low-power applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Low-power global/rolling shutter image sensors in silicon on sapphire technology.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
An efficient implementation of D-Flip-Flop using the GDI technique.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

High speed and high resolution current winner-take-all circuit in conjunction with adaptive thresholding.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Widening the dynamic range of the readout integration circuit for uncooled microbolometer infrared sensors.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

VLSI sensor for multiple targets detection and tracking.
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

High speed and high resolution current loser-take-all circuit of O(N) complexity.
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

Ultra low-power DFF based shift registers design for CMOS image sensors applications.
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

Low power global shutter CMOS active pixel image sensor with ultra-high dynamic range.
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

2003
An adaptive center of mass detection system employing a 2-D dynamic element matching algorithm for object tracking.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002
Gate-diffusion input (GDI): a power-efficient method for digital combinatorial circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2002

Gate-diffusion input (GDI) - a technique for low power design of digital circuits: analysis and characterization.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001
CMOS current/voltage mode winner-take-all circuit with spatial filtering.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001


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