Saugata Ghose
Orcid: 0000-0002-9138-0613
According to our database1,
Saugata Ghose
authored at least 98 papers
between 2009 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2024
MIMDRAM: An End-to-End Processing-Using-DRAM System for High-Throughput, Energy-Efficient and Programmer-Transparent Multiple-Instruction Multiple-Data Processing.
CoRR, 2024
MIMDRAM: An End-to-End Processing-Using-DRAM System for High-Throughput, Energy-Efficient and Programmer-Transparent Multiple-Instruction Multiple-Data Computing.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024
2023
Extending Memory Capacity in Modern Consumer Systems With Emerging Non-Volatile Memory: Experimental Analysis and Characterization Using the Intel Optane SSD.
IEEE Access, 2023
2022
Accelerating Neural Network Inference With Processing-in-DRAM: From the Edge to the Cloud.
IEEE Micro, 2022
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022
Enabling High-Performance and Energy-Efficient Hybrid Transactional/Analytical Databases with Hardware/Software Cooperation.
CoRR, 2022
Methodologies, Workloads, and Tools for Processing-in-Memory: Enabling the Adoption of Data-Centric Architectures.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
Heterogeneous Data-Centric Architectures for Modern Data-Intensive Applications: Case Studies in Machine Learning and Databases.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
SeGraM: a universal hardware accelerator for genomic sequence-to-graph and sequence-to-sequence mapping.
Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022
Polynesia: Enabling High-Performance and Energy-Efficient Hybrid Transactional/Analytical Databases with Hardware/Software Co-Design.
Proceedings of the 38th IEEE International Conference on Data Engineering, 2022
2021
Extending Memory Capacity in Consumer Devices with Emerging Non-Volatile Memory: An Experimental Study.
CoRR, 2021
Polynesia: Enabling Effective Hybrid Transactional/Analytical Databases with Specialized Hardware/Software Co-Design.
CoRR, 2021
Mitigating Edge Machine Learning Inference Bottlenecks: An Empirical Study on Accelerating Google Edge Models.
CoRR, 2021
DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks.
IEEE Access, 2021
Mentoring Opportunities in Computer Architecture: Analyzing the Past to Develop the Future.
Proceedings of the ACM/IEEE Workshop on Computer Architecture Education, 2021
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021
CODIC: A Low-Cost Substrate for Enabling Custom In-DRAM Functionalities and Optimizations.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021
BlockHammer: Preventing RowHammer at Low Cost by Blacklisting Rapidly-Accessed DRAM Rows.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021
Proceedings of the ASPLOS '21: 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2021
Google Neural Network Models for Edge Devices: Analyzing and Mitigating Machine Learning Inference Bottlenecks.
Proceedings of the 30th International Conference on Parallel Architectures and Compilation Techniques, 2021
2020
FIGARO: Improving System Performance via Fine-Grained In-DRAM Data Relocation and Caching.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020
GenASM: A High-Performance, Low-Power Approximate String Matching Acceleration Framework for Genome Sequence Analysis.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020
The Virtual Block Interface: A Flexible Alternative to the Conventional Virtual Memory Framework.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020
2019
Proc. ACM Meas. Anal. Comput. Syst., 2019
Microprocess. Microsystems, 2019
CoRR, 2019
Understanding the Interactions of Workloads and DRAM Types: A Comprehensive Experimental Study.
CoRR, 2019
Nanopore sequencing technology and tools for genome assembly: computational analysis of the current state, bottlenecks and future directions.
Briefings Bioinform., 2019
CROW: a low-cost substrate for improving DRAM performance, energy efficiency, and reliability.
Proceedings of the 46th International Symposium on Computer Architecture, 2019
Proceedings of the 46th International Symposium on Computer Architecture, 2019
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
2018
Mosaic: Enabling Application-Transparent Support for Multiple Page Sizes in Throughput Processors.
ACM SIGOPS Oper. Syst. Rev., 2018
Improving 3D NAND Flash Memory Lifetime by Tolerating Early Retention Loss and Process Variation.
Proc. ACM Meas. Anal. Comput. Syst., 2018
What Your DRAM Power Models Are Not Telling You: Lessons from a Detailed Experimental Study.
Proc. ACM Meas. Anal. Comput. Syst., 2018
Enabling Efficient RDMA-based Synchronous Mirroring of Persistent Memory Transactions.
CoRR, 2018
Techniques for Efficiently Handling Power Surges in Fuel Cell Powered Data Centers: Modeling, Analysis, Results.
CoRR, 2018
Recent Advances in Overcoming Bottlenecks in Memory Systems and Managing Memory Resources in GPU Systems.
CoRR, 2018
Characterizing, Exploiting, and Mitigating Vulnerabilities in MLC NAND Flash Memory Programming.
CoRR, 2018
CoRR, 2018
LISA: Increasing Internal Connectivity in DRAM for Fast Data Movement and Low Latency.
CoRR, 2018
Voltron: Understanding and Exploiting the Voltage-Latency-Reliability Trade-Offs in Modern DRAM Chips to Improve Energy Efficiency.
CoRR, 2018
Flexible-Latency DRAM: Understanding and Exploiting Latency Variation in Modern DRAM Chips.
CoRR, 2018
Experimental Characterization, Optimization, and Recovery of Data Retention Errors in MLC NAND Flash Memory.
CoRR, 2018
Decoupling GPU Programming Models from Resource Management for Enhanced Programming Ease, Portability, and Performance.
CoRR, 2018
Mosaic: An Application-Transparent Hardware-Software Cooperative Memory Manager for GPUs.
CoRR, 2018
Holistic Management of the GPGPU Memory Hierarchy to Manage Warp-level Latency Tolerance.
CoRR, 2018
Zorua: Enhancing Programming Ease, Portability, and Performance in GPUs by Decoupling Programming Models from Resource Management.
CoRR, 2018
Enabling the Adoption of Processing-in-Memory: Challenges, Mechanisms, Future Research Directions.
CoRR, 2018
GRIM-Filter: Fast seed location filtering in DNA read mapping using processing-in-memory technologies.
BMC Genom., 2018
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018
HeatWatch: Improving 3D NAND Flash Memory Device Reliability by Exploiting Self-Recovery and Temperature Awareness.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018
Proceedings of the 16th USENIX Conference on File and Storage Technologies, 2018
Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018
Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018
2017
Design-Induced Latency Variation in Modern DRAM Chips: Characterization, Analysis, and Latency Reduction Mechanisms.
Proc. ACM Meas. Anal. Comput. Syst., 2017
Understanding Reduced-Voltage Operation in Modern DRAM Devices: Experimental Characterization, Analysis, and Mechanisms.
Proc. ACM Meas. Anal. Comput. Syst., 2017
Error Characterization, Mitigation, and Recovery in Flash-Memory-Based Solid-State Drives.
Proc. IEEE, 2017
Improving the reliability of chip-off forensic analysis of NAND flash memory devices.
Digit. Investig., 2017
CoRR, 2017
CoRR, 2017
Understanding Reduced-Voltage Operation in Modern DRAM Chips: Characterization, Analysis, and Mechanisms.
CoRR, 2017
LazyPIM: Efficient Support for Cache Coherence in Processing-in-Memory Architectures.
CoRR, 2017
IEEE Comput. Archit. Lett., 2017
Mosaic: a GPU memory manager with application-transparent support for multiple page sizes.
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017
Carpool: a bufferless on-chip network supporting adaptive multicast and hotspot alleviation.
Proceedings of the International Conference on Supercomputing, 2017
SoftMC: A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies.
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017
Vulnerabilities in MLC NAND Flash Memory Programming: Experimental Analysis, Exploits, and Mitigation Techniques.
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017
Proceedings of the 2017 IEEE International Conference on Cluster Computing, 2017
2016
ACM Trans. Archit. Code Optim., 2016
Enabling Accurate and Practical Online Flash Channel Modeling for Modern MLC NAND Flash Memory.
IEEE J. Sel. Areas Commun., 2016
CoRR, 2016
Reducing DRAM Latency by Exploiting Design-Induced Latency Variation in Modern DRAM Chips.
CoRR, 2016
Understanding Latency Variation in Modern DRAM Chips: Experimental Characterization, Analysis, and Optimization.
Proceedings of the 2016 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Science, 2016
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016
A model for Application Slowdown Estimation in on-chip networks and its use for improving system fairness and performance.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016
Accelerating pointer chasing in 3D-stacked memory: Challenges, mechanisms, evaluation.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016
Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016
Low-Cost Inter-Linked Subarrays (LISA): Enabling fast inter-subarray data movement in DRAM.
Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016
2015
CoRR, 2015
Simultaneous Multi Layer Access: A High Bandwidth and Low Cost 3D-Stacked Memory Interface.
CoRR, 2015
WARM: Improving NAND flash memory lifetime with write-hotness aware retention management.
Proceedings of the IEEE 31st Symposium on Mass Storage Systems and Technologies, 2015
Read Disturb Errors in MLC NAND Flash Memory: Characterization, Mitigation, and Recovery.
Proceedings of the 45th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2015
Proceedings of the 2015 International Conference on Parallel Architectures and Compilation, 2015
2013
Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013
2012
Overcoming single-thread performance hurdles in the core fusion reconfigurable multicore architecture.
Proceedings of the International Conference on Supercomputing, 2012
2009
Proceedings of the Design, Automation and Test in Europe, 2009