Nuno Lourenço

Orcid: 0000-0002-9625-6435

Affiliations:
  • University of Lisbon, Portugal


According to our database1, Nuno Lourenço authored at least 78 papers between 2005 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Online presence:

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Bibliography

2024
Design Automation of Analog and Mixed-Signal Circuits Using Neural Networks - A Tutorial Brief.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024

2023
Behavioral Analysis of Noise and Bandwidth Specifications of Heartbeat Detection Circuits for Ultra Low Power Devices.
IEEE Access, 2023

Analog Integrated Circuit Routing Techniques: An Extensive Review.
IEEE Access, 2023

Design Space Exploration of Single-Stage OTAs towards an Ultra-Low-Power LNA for ECG Signals.
Proceedings of the 19th International Conference on Synthesis, 2023

A 23.5-32.5GHz, 17dBm PSAT and 37.5% PAE Power Amplifier Synthesized Using an Automated Design Methodology.
Proceedings of the 19th International Conference on Synthesis, 2023

An ANN-Based Approach to the Modelling and Simulation of Analogue Circuits.
Proceedings of the 19th International Conference on Synthesis, 2023

Efficient Hierarchical mm-Wave System Synthesis with Embedded Accurate Transformer and Balun Machine Learning Models.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022
Scalable and order invariant analog integrated circuit placement with Attention-based Graph-to-Sequence deep models.
Expert Syst. Appl., 2022

DeepPlacer: A custom integrated OpAmp placement tool using deep models.
Appl. Soft Comput., 2022

Architectural Design for Heartbeat Detection Circuits using Verilog-A Behavioral Modeling.
Proceedings of the 18th International Conference on Synthesis, 2022

Machine Learning Approaches for Transformer Modeling.
Proceedings of the 18th International Conference on Synthesis, 2022

Accelerating Voltage-Controlled Oscillator Sizing Optimizations with ANN-based Convergence Classifiers and Frequency Guess Predictors.
Proceedings of the 18th International Conference on Synthesis, 2022

ANN-based Analog IC Floorplan Recommender with a Broader Topological Constraints Coverage.
Proceedings of the 18th International Conference on Synthesis, 2022

Radiation-Hardened Bandgap Voltage and Current Reference for Space Applications with 2.38 ppm/°C Temperature Coefficient.
Proceedings of the 18th International Conference on Synthesis, 2022

Speeding-Up Complex RF IC Sizing Optimizations with a Process, Voltage and Temperature Corner Performance Estimator based on ANNs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A Radiation-Hardened Frequency-Locked Loop On-Chip Oscillator with 33.6ppm/°C Stability for Space Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Automatic Design of High-Gain 26.5-to-29.5-GHz Transformer-Less Low-Noise Amplifier 1.86-to-8.87-mW Variants in 65-nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021
Review: Machine learning techniques in analog/RF integrated circuit design, synthesis, layout, and test.
Integr., 2021

Shortening the gap between pre- and post-layout analog IC performance by reducing the LDE-induced variations with multi-objective simulated quantum annealing.
Eng. Appl. Artif. Intell., 2021

In-Depth Design Space Exploration of 26.5-to-29.5-GHz 65-nm CMOS Low-Noise Amplifiers for Low-Footprint-and-Power 5G Communications Using One-and- Two -Step Design Optimization.
IEEE Access, 2021

Hierarchical Yield-Aware Synthesis Methodology Covering Device-, Circuit-, and System-Level for Radiofrequency ICs.
IEEE Access, 2021

Late Breaking Results: Attention in Graph2Seq Neural Networks towards Push-Button Analog IC Placement.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020
A Folded Voltage-Combiners Biased Amplifier for Low Voltage and High Energy-Efficiency Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

Design of a 4.2-to-5.1 GHz Ultralow-Power Complementary Class-B/C Hybrid-Mode VCO in 65-nm CMOS Fully Supported by EDA Tools.
IEEE Trans. Circuits Syst., 2020

FUZYE: A Fuzzy <i>c</i>-Means Analog IC Yield Optimization Using Evolutionary-Based Algorithms.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Sub-μW Tow-Thomas based biquad filter with improved gain for biomedical applications.
Microelectron. J., 2020

A new family of CMOS inverter-based OTAs for biomedical and healthcare applications.
Integr., 2020

Ready-to-Fabricate RF Circuit Synthesis Using a Layout- and Variability-Aware Optimization-Based Methodology.
IEEE Access, 2020

Semi-Supervised Artificial Neural Networks towards Analog IC Placement Recommender.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Analog IC Placement Generation via Neural Networks from Unlabeled Data
Springer, ISBN: 978-3-030-50060-3, 2020

2019
Many-Objective Sizing Optimization of a Class-C/D VCO for Ultralow-Power IoT and Ultralow-Phase-Noise Cellular Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Two-Step RF IC Block Synthesis With Preoptimized Inductors and Full Layout Generation In-the-Loop.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

A Low Noise CMOS Inverter-Based OTA for and Healthcare Signal Receivers.
Proceedings of the 16th International Conference on Synthesis, 2019

Artificial Neural Networks as an Alternative for Automatic Analog IC Placement.
Proceedings of the 16th International Conference on Synthesis, 2019

Using Polynomial Regression and Artificial Neural Networks for Reusable Analog IC Sizing.
Proceedings of the 16th International Conference on Synthesis, 2019

On the Exploration of Design Tradeoffs in Analog IC Placement with Layout-dependent Effects.
Proceedings of the 16th International Conference on Synthesis, 2019

Using EDA Tools to Push the Performance Boundaries of an Ultralow-Power IoT-VCO at 65nm.
Proceedings of the 16th International Conference on Synthesis, 2019

Hard and Soft Constraints for Multi-objective Analog IC Sizing Optimization.
Proceedings of the 16th International Conference on Synthesis, 2019

2018
Single-Stage OTA Biased by Voltage-Combiners With Enhanced Performance Using Current Starving.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

Single-Stage Amplifier Biased by Voltage Combiners With Gain and Energy-Efficiency Enhancement.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

Enhanced systematic design of a voltage controlled oscillator using a two-step optimization methodology.
Integr., 2018

Handling the Effects of Variability and Layout Parasitics in the Automatic Synthesis of LNAs.
Proceedings of the 15th International Conference on Synthesis, 2018

A 20 DB Gain Two-Stage Low-Noise Amplifier with High Yield for 5 GHz Applications.
Proceedings of the 15th International Conference on Synthesis, 2018

On the Exploration of Promising Analog IC Designs via Artificial Neural Networks.
Proceedings of the 15th International Conference on Synthesis, 2018

Design and Optimization of a Class-C/D VCO for Ultra-Low-Power IoT and Cellular Applications.
Proceedings of the 15th International Conference on Synthesis, 2018

Enhanced analog and RF IC sizing methodology using PCA and NSGA-II optimization kernel.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Stochastic-based placement template generator for analog IC layout-aware synthesis.
Integr., 2017

Systematic design of a voltage controlled oscillator using a layout-aware approach.
Proceedings of the 14th International Conference on Synthesis, 2017

Layout-aware challenges and a solution for the automatic synthesis of radio-frequency IC blocks.
Proceedings of the 14th International Conference on Synthesis, 2017

New mapping strategies for pre-optimized inductor sets in bottom-up RF IC sizing optimization.
Proceedings of the 14th International Conference on Synthesis, 2017

Efficient yield optimization method using a variable K-Means algorithm for analog IC sizing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Automatic technology migration of analog IC designs using generic cell libraries.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
Automatic synthesis of RF front-end blocks using multi-objective evolutionary techniques.
Integr., 2016

Design and application of a CMOS active inductor at Ku band based on a multi-objective optimizer.
Integr., 2016

Current-flow and current-density-aware multi-objective optimization of analog IC placement.
Integr., 2016

AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation.
Integr., 2016

Automated analog IC design constraints generation for a layout-aware sizing approach.
Proceedings of the 13th International Conference on Synthesis, 2016

Yield optimization using k-means clustering algorithm to reduce Monte Carlo simulations.
Proceedings of the 13th International Conference on Synthesis, 2016

On-the-fly exploration of placement templates for analog IC layout-aware sizing methodologies.
Proceedings of the 13th International Conference on Synthesis, 2016

Design automation tasks scheduling for enhanced parallel execution of a state-of-the-art layout-aware sizing approach.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Floorplan-aware analog IC sizing and optimization based on topological constraints.
Integr., 2015

Multi-objective optimization of analog integrated circuit placement hierarchy in absolute coordinates.
Expert Syst. Appl., 2015

A voltage-combiners-biased amplifier with enhanced gain and speed using current starving.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Extraction and application of wiring symmetry rules to route analog multiport terminals.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Layout-aware sizing of analog ICs using floorplan & routing estimates for parasitic extraction.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Electromigration-aware analog Router with multilayer multiport terminal structures.
Integr., 2014

LC-VCO automatic synthesis using multi-objective evolutionary techniques.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A cascode-free single-stage amplifier using a fully-differential folded voltage-combiner.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

Electromigration-aware and IR-Drop avoidance routing in analog multiport terminal structures.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
LAYGEN II - Automatic Layout Generation of Analog Integrated Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Single-stage amplifiers with gain enhancement and improved energy-efficiency employing voltage-combiners.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Enhancing a Layout-Aware Synthesis Methodology for Analog ICs by Embedding Statistical Knowledge into the Evolutionary Optimization Kernel.
Proceedings of the Technological Innovation for the Internet of Things, 2013

A new metaheuristc combining gradient models with NSGA-II to enhance analog IC synthesis.
Proceedings of the IEEE Congress on Evolutionary Computation, 2013

Multi-port multi-terminal analog router based on an evolutionary optimization kernel.
Proceedings of the IEEE Congress on Evolutionary Computation, 2013

2012
LAYGEN II: automatic analog ICs layout generator based on a template approach.
Proceedings of the Genetic and Evolutionary Computation Conference, 2012

GENOM-POF: multi-objective evolutionary synthesis of analog ICs with corners validation.
Proceedings of the Genetic and Evolutionary Computation Conference, 2012

2007
Automatic analog IC layout generation based on a evolutionary computation approach.
Proceedings of the Genetic and Evolutionary Computation Conference, 2007

2005
Laygen - An evolutionary approach to automatic analog IC layout generation.
Proceedings of the 12th IEEE International Conference on Electronics, 2005


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