Panagiotis Athanasopoulos

According to our database, Panagiotis Athanasopoulos authored at least 9 papers between 2008 and 2013.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2013

3D-MMC: a modular 3D multi-core architecture with efficient resource pooling.

Tiansheng Zhang, Alessandro Cevrero, Giulia Beanato, Panagiotis Athanasopoulos, Ayse K. Coskun, Yusuf Leblebici

Proceedings of the Design, Automation and Test in Europe, 2013

2012

Design and Testing Strategies for Modular 3-D-Multiprocessor Systems Using Die-Level Through Silicon Via Technology.

Giulia Beanato, Paolo Giovannini, Alessandro Cevrero, Panagiotis Athanasopoulos, Michael Zervas, Yuksel Temiz, Yusuf Leblebici

IEEE J. Emerg. Sel. Topics Circuits Syst., 2012

2010

Design and feasibility of multi-Gb/s quasi-serial vertical interconnects based on TSVs for 3D ICs.

Fengda Sun, Alessandro Cevrero, Panagiotis Athanasopoulos, Yusuf Leblebici

Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

2009

Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs.

Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay Kumar Verma, Seyed-Hosein Attarzadeh-Niaki, Chrysostomos Nicopoulos, Frank K. Gürkaynak, Philip Brisk, Yusuf Leblebici, Paolo Ienne

ACM Trans. Reconfigurable Technol. Syst., 2009

Memory organization and data layout for instruction set extensions with architecturally visible storage.

Panagiotis Athanasopoulos, Philip Brisk, Yusuf Leblebici, Paolo Ienne

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

A flexible DSP block to enhance FPGA arithmetic performance.

Hadi Parandeh-Afshar, Alessandro Cevrero, Panagiotis Athanasopoulos, Philip Brisk, Yusuf Leblebici, Paolo Ienne

Proceedings of the 2009 International Conference on Field-Programmable Technology, 2009

Using 3D integration technology to realize multi-context FPGAs.

Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Maurizio Skerlj, Philip Brisk, Yusuf Leblebici, Paolo Ienne

Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

3D configuration caching for 2D FPGAs.

Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Philip Brisk, Yusuf Leblebici, Paolo Ienne, Maurizio Skerlj

Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

2008

Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs.

Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay Kumar Verma, Philip Brisk, Frank K. Gürkaynak, Yusuf Leblebici, Paolo Ienne

Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, 2008