Hadi Parandeh-Afshar

According to our database, Hadi Parandeh-Afshar authored at least 29 papers between 2006 and 2018.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2018

Approximate quaternary addition with the fast carry chains of FPGAs.

Sina Boroumand, Hadi Parandeh-Afshar, Philip Brisk

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Exploration of approximate multipliers design space using carry propagation free compressors.

Sina Boroumand, Hadi Parandeh-Afshar, Philip Brisk, Siamak Mohammadi

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017

CAL: Exploring cost, accuracy, and latency in approximate and speculative adder design.

Sina Boroumand, Hadi Parandeh-Afshar, Philip Brisk, Siamak Mohammadi

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

2014

Revisiting and-inverter cones.

Grace Zgheib, Liqun Yang, Zhihong Huang, David Novo, Hadi Parandeh-Afshar, Haigang Yang, Paolo Ienne

Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

2013

Shadow And-Inverter Cones.

Hadi Parandeh-Afshar, Grace Zgheib, David Novo, Madhura Purnaprajna, Paolo Ienne

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Shadow AICs: reaping the benefits of and-inverter cones with minimal architectural impact (abstract only).

Hadi Parandeh-Afshar, Grace Zgheib, David Novo, Madhura Purnaprajna, Paolo Ienne

Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

2012

Closing the Gap between FPGA and ASIC - Balancing Flexibility and Efficiency.

Hadi Parandeh-Afshar

PhD thesis, 2012

Rethinking FPGAs: elude the flexibility excess of LUTs with and-inverter cones.

Hadi Parandeh-Afshar, Hind Benbihi, David Novo, Paolo Ienne

Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

Reducing the cost of floating-point mantissa alignment and normalization in FPGAs.

Yehdhih Ould Mohammed Moctar, Nithin George, Hadi Parandeh-Afshar, Paolo Ienne, Guy G. F. Lemieux, Philip Brisk

Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

2011

Compressor tree synthesis on commercial high-performance FPGAs.

Hadi Parandeh-Afshar, Arkosnato Neogy, Philip Brisk, Paolo Ienne

ACM Trans. Reconfigurable Technol. Syst., 2011

Measuring and Reducing the Performance Gap between Embedded and Soft Multipliers on FPGAs.

Hadi Parandeh-Afshar, Paolo Ienne

Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

Reducing the pressure on routing resources of FPGAs with generic logic chains.

Hadi Parandeh-Afshar, Grace Zgheib, Philip Brisk, Paolo Ienne

Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

2010

Improving FPGA Performance for Carry-Save Arithmetic.

Hadi Parandeh-Afshar, Ajay Kumar Verma, Philip Brisk, Paolo Ienne

IEEE Trans. Very Large Scale Integr. Syst., 2010

Synthesis of Floating-Point Addition Clusters on FPGAs Using Carry-Save Arithmetic.

Amit Verma, Ajay Kumar Verma, Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne

Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

Highly Versatile DSP Blocks for Improved FPGA Arithmetic Performance.

Hadi Parandeh-Afshar, Paolo Ienne

Proceedings of the 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2010

2009

An FPGA Logic Cell and Carry Chain Configurable as a 6: 2 or 7: 2 Compressor.

Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne

ACM Trans. Reconfigurable Technol. Syst., 2009

Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs.

Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay Kumar Verma, Seyed-Hosein Attarzadeh-Niaki, Chrysostomos Nicopoulos, Frank K. Gürkaynak, Philip Brisk, Yusuf Leblebici, Paolo Ienne

ACM Trans. Reconfigurable Technol. Syst., 2009

A flexible DSP block to enhance FPGA arithmetic performance.

Hadi Parandeh-Afshar, Alessandro Cevrero, Panagiotis Athanasopoulos, Philip Brisk, Yusuf Leblebici, Paolo Ienne

Proceedings of the 2009 International Conference on Field-Programmable Technology, 2009

Exploiting fast carry-chains of FPGAs for designing compressor trees.

Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne

Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Using 3D integration technology to realize multi-context FPGAs.

Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Maurizio Skerlj, Philip Brisk, Yusuf Leblebici, Paolo Ienne

Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

3D configuration caching for 2D FPGAs.

Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Philip Brisk, Yusuf Leblebici, Paolo Ienne, Maurizio Skerlj

Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

2008

A novel FPGA logic block for improved arithmetic performance.

Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne

Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, 2008

Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs.

Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay Kumar Verma, Philip Brisk, Frank K. Gürkaynak, Yusuf Leblebici, Paolo Ienne

Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, 2008

Improving Synthesis of Compressor Trees on FPGAs via Integer Linear Programming.

Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne

Proceedings of the Design, Automation and Test in Europe, 2008

Efficient synthesis of compressor trees on FPGAs.

Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007

Fast INC-XOR codec for low-power address buses.

Hadi Parandeh-Afshar, Mohsen Saneei, Ali Afzali-Kusha, Massoud Pedram

IET Comput. Digit. Tech., 2007

Enhancing FPGA Performance for Arithmetic Circuits.

Philip Brisk, Ajay Kumar Verma, Paolo Ienne, Hadi Parandeh-Afshar

Proceedings of the 44th Design Automation Conference, 2007

2006

A very high performance address BUS encoder.

Hadi Parandeh-Afshar, Ali Afzali-Kusha, Ali Khaki-Firooz

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A Novel Merged Multiplier-Accumulator Embedded in DSP Coprocessor.

Hadi Parandeh-Afshar, Mohsen Ahmadvand, Saeed Safari

Proceedings of the 13th IEEE International Conference on Electronics, 2006