Giulia Beanato

According to our database, Giulia Beanato authored at least 7 papers between 2012 and 2016.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2016

Design and analysis of jitter-aware low-power and high-speed TSV link for 3D ICs.

Giulia Beanato, Kiarash Gharibdoust, Alessandro Cevrero, Giovanni De Micheli, Yusuf Leblebici

Microelectron. J., 2016

Impact of data serialization over TSVs on routing congestion in 3D-stacked multi-core processors.

Giulia Beanato, Alessandro Cevrero, Giovanni De Micheli, Yusuf Leblebici

Microelectron. J., 2016

2014

3D serial TSV link for low-power chip-to-chip communication.

Giulia Beanato, Alessandro Cevrero, Giovanni De Micheli, Yusuf Leblebici

Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014

2013

3D-MMC: a modular 3D multi-core architecture with efficient resource pooling.

Tiansheng Zhang, Alessandro Cevrero, Giulia Beanato, Panagiotis Athanasopoulos, Ayse K. Coskun, Yusuf Leblebici

Proceedings of the Design, Automation and Test in Europe, 2013

2012

Design and Testing Strategies for Modular 3-D-Multiprocessor Systems Using Die-Level Through Silicon Via Technology.

Giulia Beanato, Paolo Giovannini, Alessandro Cevrero, Panagiotis Athanasopoulos, Michael Zervas, Yuksel Temiz, Yusuf Leblebici

IEEE J. Emerg. Sel. Topics Circuits Syst., 2012

Configurable Low-Latency Interconnect for Multi-core Clusters.

Giulia Beanato, Igor Loi, Giovanni De Micheli, Yusuf Leblebici, Luca Benini

Proceedings of the VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design, 2012

3D-LIN: A configurable low-latency interconnect for multi-core clusters with 3D stacked L1 memory.

Giulia Beanato, Igor Loi, Giovanni De Micheli, Yusuf Leblebici, Luca Benini

Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012