Partho Bhoumik
Orcid: 0009-0006-4722-1910
According to our database1,
Partho Bhoumik authored at least 11 papers
between 2024 and 2026.
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Bibliography
2026
Defect-Aware Built-In Self-Test and Dynamic Repair for Fan-Out Wafer-Level Packaging.
IEEE Trans. Very Large Scale Integr. Syst., March, 2026
NERT: Network- and Routing-aware Testing of Interconnects in Fanout Wafer-Level Packaging.
Proceedings of the 44th IEEE VLSI Test Symposium, 2026
Proceedings of the 44th IEEE VLSI Test Symposium, 2026
Proceedings of the 44th IEEE VLSI Test Symposium, 2026
2025
Defect Analysis and Built-In-Self-Test for Chiplet Interconnects in Fan-out Wafer-Level Packaging.
CoRR, March, 2025
Defect Analysis and Built-In-Self-Test for Chiplet Interconnects in Fan-out Wafer-Level Packaging<sup>*</sup>.
Proceedings of the 43rd IEEE VLSI Test Symposium, 2025
SMART: Scalable and Modular Architecture for Routing-Aware Testing of Fan-out Wafer-Level Packages<sup>*</sup>.
Proceedings of the IEEE International Test Conference, 2025
Fault Modeling and Testing of Chiplet-to-Chiplet Interconnects in Fan-out Wafer-Level Packaging<sup>*</sup>.
Proceedings of the IEEE International Test Conference, 2025
The Unlikely Hero: Nonidealities in Analog Photonic Neural Networks as Built-in Adversarial Defenders.
Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025
2024
The Unlikely Hero: Nonideality in Analog Photonic Neural Networks as Built-in Defender Against Adversarial Attacks.
CoRR, 2024
Testing and Fault Diagnosis for Multi-level Resistive Random-Access Memory in Monolithic 3D Integration.
Proceedings of the 42nd IEEE VLSI Test Symposium, 2024