Shao-Chun Hung

Orcid: 0000-0003-1125-6709

According to our database1, Shao-Chun Hung authored at least 15 papers between 2019 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Fault Diagnosis for Resistive Random Access Memory and Monolithic Inter-Tier Vias in Monolithic 3-D Integration.
IEEE Trans. Very Large Scale Integr. Syst., July, 2024

Testing and Fault Diagnosis for Multi-level Resistive Random-Access Memory in Monolithic 3D Integration.
Proceedings of the 42nd IEEE VLSI Test Symposium, 2024

2023
Transferable Graph Neural Network-Based Delay-Fault Localization for Monolithic 3-D ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

Special Session: Using Graph Neural Networks for Tier-Level Fault Localization in Monolithic 3D ICs <sup>*</sup>.
Proceedings of the 41st IEEE VLSI Test Symposium, 2023

Scan Cell Segmentation Based on Reinforcement Learning for Power-Safe Testing of Monolithic 3D ICs.
Proceedings of the IEEE International Test Conference, 2023

Test-Point Insertion for Power-Safe Testing of Monolithic 3D ICs using Reinforcement Learning<sup>*</sup>.
Proceedings of the IEEE European Test Symposium, 2023

2022
Fault Diagnosis for Resistive Random-Access Memory and Monolithic Inter-tier Vias in Monolithic 3D Integration.
Proceedings of the IEEE International Test Conference, 2022

Observation Point Insertion Using Deep Learning.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

Graph Neural Network-based Delay-Fault Localization for Monolithic 3D ICs.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021
Power Supply Noise-Aware At-Speed Delay Fault Testing of Monolithic 3-D ICs.
IEEE Trans. Very Large Scale Integr. Syst., 2021

A DAG-Based Algorithm for Obstacle-Aware Topology-Matching On-Track Bus Routing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Advances in Testing and Design-for-Test Solutions for M3D Integrated Circuits.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
Design of a Reliable Power Delivery Network for Monolithic 3D ICs<sup>*</sup>.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Power Supply Noise-Aware Scan Test Pattern Reshaping for At-Speed Delay Fault Testing of Monolithic 3D ICs <sup>*</sup>.
Proceedings of the 29th IEEE Asian Test Symposium, 2020

2019
Disjoint-Support Decomposition and Extraction for Interconnect-Driven Threshold Logic Synthesis.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019


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