Thomas Christoph Müller

According to our database, Thomas Christoph Müller authored at least 8 papers between 2016 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

X-HEEP: An Open-Source, Configurable and Extendible RISC-V Microcontroller for the Exploration of Ultra-Low-Power Edge Accelerators.

Simone Machetti, Pasquale Davide Schiavone, Thomas Christoph Müller, Miguel Peón Quirós, David Atienza

CoRR, 2024

2023

X-HEEP: An Open-Source, Configurable and Extendible RISC-V Microcontroller.

Pasquale Davide Schiavone, Simone Machetti, Miguel Peón Quirós, Jose Miranda, Benoît W. Denkinger, Thomas Christoph Müller, Ruben Rodríguez, Saverio Nasturzio, David Atienza Alonso

Proceedings of the 20th ACM International Conference on Computing Frontiers, 2023

2018

A 588-Gb/s LDPC Decoder Based on Finite-Alphabet Message Passing.

Reza Ghanaatian, Alexios Balatsoukas-Stimming, Thomas Christoph Müller, Michael Meidlinger, Gerald Matz, Adam Teman, Andreas Burg

IEEE Trans. Very Large Scale Integr. Syst., 2018

2017

PolarBear: A 28-nm FD-SOI ASIC for Decoding of Polar Codes.

Pascal Giard, Alexios Balatsoukas-Stimming, Thomas Christoph Müller, Andrea Bonetti, Claude Thibeault, Warren J. Gross, Philippe Flatresse, Andreas Burg

IEEE J. Emerg. Sel. Topics Circuits Syst., 2017

A Self-Aware Architecture for PVT Compensation and Power Nap in Near Threshold Processors.

Davide Rossi, Igor Loi, Antonio Pullini, Thomas Christoph Müller, Andreas Burg, Francesco Conti, Luca Benini, Philippe Flatresse

IEEE Des. Test, 2017

A 594 Gbps LDPC Decoder Based on Finite-Alphabet Message Passing.

Reza Ghanaatian, Alexios Balatsoukas-Stimming, Thomas Christoph Müller, Michael Meidlinger, Gerald Matz, Adam Teman, Andreas Burg

CoRR, 2017

2016

DynOR: A 32-bit microprocessor in 28 nm FD-SOI with cycle-by-cycle dynamic clock adjustment.

Jeremy Constantin, Andrea Bonetti, Adam Teman, Thomas Christoph Müller, Lorenz Schmid, Andreas Burg

Proceedings of the ESSCIRC Conference 2016: 42^nd European Solid-State Circuits Conference, 2016

A multi-Gbps unrolled hardware list decoder for a systematic polar code.

Pascal Giard, Alexios Balatsoukas-Stimming, Thomas Christoph Müller, Andreas Peter Burg, Claude Thibeault, Warren J. Gross

Proceedings of the 50th Asilomar Conference on Signals, Systems and Computers, 2016