Sanjay V. Rajopadhye

According to our database1, Sanjay V. Rajopadhye
  • authored at least 99 papers between 1985 and 2017.
  • has a "Dijkstra number"2 of four.

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Bibliography

2017
Simple, Accurate, Analytical Time Modeling and Optimal Tile Size Selection for GPGPU Stencils.
Proceedings of the 22nd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2017

One size does not fit all: Implementation trade-offs for iterative stencil computations on FPGAs.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

2016
Hybrid Static/Dynamic Schedules for Tiled Polyhedral Programs.
CoRR, 2016

2015
Combining execution pipelines to improve parallel implementation of HMMER on FPGA.
Microprocessors and Microsystems - Embedded Hardware Design, 2015

Energy Modeling and Optimization for Tiled Nested-Loop Codes.
Proceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium Workshop, 2015

Automatic Energy Efficient Parallelization of Uniform Dependence Computations.
Proceedings of the 29th ACM on International Conference on Supercomputing, 2015

2014
On Program Equivalence with Reductions.
Proceedings of the Static Analysis - 21st International Symposium, 2014

Optimizing Dynamic Resource Allocation.
Proceedings of the International Conference on Computational Science, 2014

2013
Checking Race Freedom of Clocked X10 Programs.
CoRR, 2013

Array dataflow analysis for polyhedral X10 programs.
Proceedings of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2013

Folklore Confirmed: Compiling for Speed = Compiling for Energy.
Proceedings of the Languages and Compilers for Parallel Computing, 2013

2012
Improving Reliability of Islanded Distribution Systems With Distributed Renewable Energy Resources.
IEEE Trans. Smart Grid, 2012

Parameterized loop tiling.
ACM Trans. Program. Lang. Syst., 2012

Bridging the chasm between MDE and the world of compilation.
Software and System Modeling, 2012

AlphaZ: A System for Design Space Exploration in the Polyhedral Model.
Proceedings of the Languages and Compilers for Parallel Computing, 2012

Scan detection and parallelization in "inherently sequential" nested loop programs.
Proceedings of the 10th Annual IEEE/ACM International Symposium on Code Generation and Optimization, 2012

2011
Model-Driven Engineering and Optimizing Compilers: A Bridge Too Far?
Proceedings of the Model Driven Engineering Languages and Systems, 2011

ompVerify: Polyhedral Analysis for the OpenMP Programmer.
Proceedings of the OpenMP in the Petascale Era - 7th International Workshop on OpenMP, 2011

Alphabets: An Extended Polyhedral Equational Language.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

Improving CUDASW++, a Parallelization of Smith-Waterman for CUDA Enabled Devices.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

2010
Accelerating HMMER on FPGA using parallel prefixes and reductions.
Proceedings of the International Conference on Field-Programmable Technology, 2010

Automatic creation of tile size selection models.
Proceedings of the CGO 2010, 2010

2009
A reindexing based approach towards mapping of DAG with affine schedules onto parallel embedded systems.
J. Parallel Distrib. Comput., 2009

Efficient Tiled Loop Generation: D-Tiling.
Proceedings of the Languages and Compilers for Parallel Computing, 2009

2008
Positivity, posynomials and tile size selection.
Proceedings of the ACM/IEEE Conference on High Performance Computing, 2008

A domain specific interconnect for reconfigurable computing.
Proceedings of the 2008 ACM SIGPLAN/SIGBED Conference on Languages, 2008

Smashing: Folding Space to Tile through Time.
Proceedings of the Languages and Compilers for Parallel Computing, 2008

2007
Special Issue on ASAP 2004 Conference.
VLSI Signal Processing, 2007

Multi-level tiling: M for the price of one.
Proceedings of the ACM/IEEE Conference on High Performance Networking and Computing, 2007

The Z-polyhedral model.
Proceedings of the 12th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2007

Parameterized tiled loops for free.
Proceedings of the ACM SIGPLAN 2007 Conference on Programming Language Design and Implementation, 2007

Towards Optimal Multi-level Tiling for Stencil Computations.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

Scheduling in the Z-Polyhedral Model.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

0/1 Knapsack on Hardware: A Complete Solution.
Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

Computations on Iteration Spaces.
The Compiler Design Handbook, 2nd ed., 2007

2006
Simplifying reductions.
Proceedings of the 33rd ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, 2006

On Control Signals for Multi-Dimensional Time.
Proceedings of the Languages and Compilers for Parallel Computing, 2006

An Improved Systolic Architecture for LU Decomposition.
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006

2005
Combined ILP and Register Tiling: Analytical Model and Optimization Framework.
Proceedings of the Languages and Compilers for Parallel Computing, 2005

A 1.5-D Architecture for Back-Propagation Training.
Proceedings of The 2005 International Conference on Engineering of Reconfigurable Systems and Algorithms, 2005

2004
A Geometric Programming Framework for Optimal Multi-Level Tiling.
Proceedings of the ACM/IEEE SC2004 Conference on High Performance Networking and Computing, 2004

2003
Optimal Semi-Oblique Tiling.
IEEE Trans. Parallel Distrib. Syst., 2003

Switched Memory Architectures-Moving Beyond Systolic Arrays.
Proceedings of the 14th IEEE International Conference on Application-Specific Systems, 2003

2002
Scheduling reductions on realistic machines.
SPAA, 2002

Energy/Power Estimation of Regular Processor Arrays.
Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

Dependence Analysis and Parallelizing Transformations.
The Compiler Design Handbook, 2002

2001
Optimal semi-oblique tiling.
SPAA, 2001

Combined instruction and loop parallelism in array synthesis for FPGAs.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Proving Properties of Multidimensional Recurrences with Application to Regular Parallel Algorithms.
Proceedings of the 15th International Parallel & Distributed Processing Symposium (IPDPS-01), 2001

Uniformization of Affine Dependance Programs for Parallel Embedded System Design.
Proceedings of the 2001 International Conference on Parallel Processing, 2001

Loop Tiling for Reconfigurable Accelerators.
Proceedings of the Field-Programmable Logic and Applications, 2001

Combining Instruction and Loop Level Parallelism for FPGAs.
Proceedings of the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2001

2000
Optimizing memory usage in the polyhedral model.
ACM Trans. Program. Lang. Syst., 2000

Derivation of systolic algorithms for the algebraic path problem by recurrence transformations.
Parallel Computing, 2000

Generation of Efficient Nested Loops from Polyhedra.
International Journal of Parallel Programming, 2000

Unbounded knapsack problem: Dynamic programming revisited.
European Journal of Operational Research, 2000

Optimal Partitioning for FPGA Based Regular Array Implementations.
Proceedings of the 2000 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2000), 2000

FCCMS and the Memory Wall.
Proceedings of the 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 2000

Quadratic Control Signals in Linear Systolic Arrays.
Proceedings of the 12th IEEE International Conference on Application-Specific Systems, 2000

1999
The Algebraic Path Problem Revisited.
Proceedings of the Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31, 1999

1998
Linear Programming Models for Scheduling Systems of Affine Recurrence Equations - A Comparative Study.
SPAA, 1998

Optimal Orthogonal Tiling.
Proceedings of the Euro-Par '98 Parallel Processing, 1998

1997
Knapsack on VLSI: from Algorithm to Optimal Circuit.
IEEE Trans. Parallel Distrib. Syst., 1997

Multirate VLSI Arrays and Their Synthesis.
IEEE Trans. Computers, 1997

Memory Reuse Analysis in the Polyhedral Model.
Parallel Processing Letters, 1997

On Manipulating Z-Polyhedra Using a Canonical Representation.
Parallel Processing Letters, 1997

Optimal Orthogonal Tiling of 2-D Iterations.
J. Parallel Distrib. Comput., 1997

1996
Parallel Divide and Conquer on Meshes.
IEEE Trans. Parallel Distrib. Syst., 1996

A Regular VLSI Array for an Irregular Algorithm.
Proceedings of the Parallel Algorithms for Irregularly Structured Problems, 1996

Two-dimensional orthogonal tiling: from theory to practice.
Proceedings of the 3rd International Conference on High Performance Computing, 1996

Memory Reuse Analysis in the Polyhedral Model.
Proceedings of the Euro-Par '96 Parallel Processing, 1996

Extension Of The Alpha Language To Recurrences On Sparse Periodic Domains.
Proceedings of the 1996 International Conference on Application-Specific Systems, 1996

1995
A Shift Registered-Based Systolic Array for the Unbounded Knapsack Problem.
Parallel Processing Letters, 1995

On deriving data parallel code from a functional program.
Proceedings of IPPS '95, 1995

Deriving Imperative Code from Functional Programs.
Proceedings of the seventh international conference on Functional programming languages and computer architecture, 1995

The naive execution of affine recurrence equations.
Proceedings of the International Conference on Application Specific Array Processors (ASAP'95), 1995

Synthesis of Multirate VLSI Arrays.
Proceedings of the International Conference on Application Specific Array Processors (ASAP'95), 1995

1994
Pure Systolic Array for a Class of Dynamic Dependency Recurrences.
Proceedings of the Parcella 1994, 1994

Optimal Tile Sizing.
Proceedings of the Parallel Processing: CONPAR 94, 1994

A sparse knapsack algo-tech-cuit and its synthesis.
Proceedings of the International Conference on Application Specific Array Processors, 1994

1993
An improved systolic algorithm for the algebraic path problem.
Integration, 1993

Analysis of Affine Communication Specifications.
Proceedings of the Fifth IEEE Symposium on Parallel and Distributed Processing, 1993

Parallel Assignment, Reduction and Communication for Data Parallel Programming.
Proceedings of the Sixth SIAM Conference on Parallel Processing for Scientific Computing, 1993

1992
Systematic generation of linear allocation functions in systolic array design.
VLSI Signal Processing, 1992

Quasi-Linear allocation functions for efficient array design.
VLSI Signal Processing, 1992

Parallel Implementation of Divide-and-Conquer Algorithms on Binary de Bruijn Networks.
Proceedings of the 6th International Parallel Processing Symposium, 1992

Reasoning about Permutations in Regular Arrays.
Proceedings of the Designing Correct Circuits, 1992

1991
OREGAMI: Tools for mapping parallel computations to parallel architectures.
International Journal of Parallel Programming, 1991

Deriving Fully Efficient Systolic Arrays by Quasi-Linear Allocation Functions.
Proceedings of the PARLE '91: Parallel Architectures and Languages Europe, 1991

An improved systolic algorithm for the algebraic path problem.
Proceedings of the Algorithms and Parallel VLSI Architectures II, 1991

1990
Synthesizing systolic arrays from recurrence equations.
Parallel Computing, 1990

Automating the design of systolic arrays.
Integration, 1990

Mapping Divide-and-Conquer Algorithms to Parallel Architectures.
Proceedings of the 1990 International Conference on Parallel Processing, 1990

OREGAMI: Software Tools for Mapping Parallel Computations to Parallel Architectures.
Proceedings of the 1990 International Conference on Parallel Processing, 1990

1989
Synthesizing Systolic Arrays with Control Signals from Recurrence Equations.
Distributed Computing, 1989

1987
Systolic Array Synthesis by Static Analysis of Program Dependencies.
Proceedings of the PARLE, 1987

1986
Verification of Systolic Arrays: A Stream Function Approach.
Proceedings of the International Conference on Parallel Processing, 1986

On Synthesizing Systolic Arrays from Recurrence Equations with Linear Dependencies.
Proceedings of the Foundations of Software Technology and Theoretical Computer Science, 1986

1985
Formal semantics for a symbolic IC design technique: Examples and applications.
Integration, 1985


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