Ing-Chao Lin

Orcid: 0000-0003-1994-7512

According to our database1, Ing-Chao Lin authored at least 46 papers between 2005 and 2023.

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Bibliography

2023
Class-Aware Pruning for Efficient Neural Networks.
CoRR, 2023

CIMulator: A Comprehensive Simulation Platform for Computing-In-Memory Circuit Macros with Low Bit-Width and Real Memory Materials.
CoRR, 2023

A Novel and Efficient Block-Based Programming for ReRAM-Based Neuromorphic Computing.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

2022
An Efficient Implementation of Convolutional Neural Network With CLIP-Q Quantization on FPGA.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

A Low-Power and High-Accuracy Approximate Multiplier With Reconfigurable Truncation.
IEEE Access, 2022

An Aging Detection and Tolerance Framework for 8T SRAM Dot Product CIM Engine.
Proceedings of the 19th International SoC Design Conference, 2022

GraphRC: Accelerating Graph Processing on Dual-Addressing Memory with Vertex Merging.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

WRAP: Weight RemApping and Processing in RRAM-based Neural Network Accelerators Considering Thermal Effect.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021
A Novel, Efficient Implementation of a Local Binary Convolutional Neural Network.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

Rescuing RRAM-Based Computing From Static and Dynamic Faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

An efficient <i>NBTI</i>-aware wake-up strategy: Concept, design, and manipulation.
Integr., 2021

Exploring Adversarial Examples for Efficient Active Learning in Machine Learning Classifiers.
CoRR, 2021

A Novel NBTI-Aware Chip Remaining Lifetime Prediction Framework Using Machine Learning.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

2020
A Novel Comparison-Free 1-D Median Filter.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

Global Clean Page First Replacement and Index-Aware Multistream Prefetcher in Hybrid Memory Architecture.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

An NBTI-aware Task Parallelism Scheme for Improving Lifespan of Multi-core Systems.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

Overview of 2020 CAD Contest at ICCAD.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

2019
Infection-Based Dead Page Prediction in Hybrid Memory Architecture.
IEEE Trans. Very Large Scale Integr. Syst., 2019

OCMAS: Online Page Clustering for Multibank Scratchpad Memory.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

TAP: Reducing the Energy of Asymmetric Hybrid Last-Level Cache via Thrashing Aware Placement and Migration.
IEEE Trans. Computers, 2019

Overview of 2019 CAD Contest at ICCAD.
Proceedings of the International Conference on Computer-Aided Design, 2019

ROAD: Improving Reliability of Multi-core System via Asymmetric Aging.
Proceedings of the International Conference on Computer-Aided Design, 2019

2018
Mitigating BTI-Induced Degradation in STT-MRAM Sensing Schemes.
IEEE Trans. Very Large Scale Integr. Syst., 2018

An efficient NBTI-aware wake-up strategy for power-gated designs.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
ROHOM: Requirement-Aware Online Hybrid On-Chip Memory Management for Multicore Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Reducing aging on scratchpad memory using temporal- and FSM-based power management.
Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017

2016
Reducing Aging Effects on Ternary CAM.
IEICE Trans. Electron., 2016

2015
High-Performance Low-Power Carry Speculative Addition With Variable Latency.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic.
IEEE Trans. Very Large Scale Integr. Syst., 2015

High-Endurance Hybrid Cache Design in CMP Architecture With Cache Partitioning and Access-Aware Policies.
IEEE Trans. Very Large Scale Integr. Syst., 2015

2014
NBTI and Leakage Reduction Using ILP-Based Approach.
IEEE Trans. Very Large Scale Integr. Syst., 2014

BTI-Aware Sleep Transistor Sizing Algorithm for Reliable Power Gating Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Capture-Power-Safe Test Pattern Determination for At-Speed Scan-Based Testing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

CASA: Contention-Aware Scratchpad Memory Allocation for Online Hybrid On-Chip Memory Management.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

NBTI tolerance and leakage reduction using gate sizing.
ACM J. Emerg. Technol. Comput. Syst., 2014

Analyzing the BTI Effect on Multi-bit Retention Registers.
Proceedings of the Intelligent Systems and Applications, 2014

2013
Leakage and Aging Optimization Using Transmission Gate-Based Technique.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Impacts of NBTI and PBTI effects on ternary CAM.
Proceedings of the International Symposium on Quality Electronic Design, 2013

High accuracy approximate multiplier with error correction.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

High-endurance hybrid cache design in CMP architecture with cache partitioning and access-aware policy.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

2012
Aging-aware reliable multiplier design.
Proceedings of the IEEE 25th International SOC Conference, 2012

2011
TG-based technique for NBTI degradation and leakage optimization.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

Analyzing throughput of power and thermal-constraint multicore processor under NBTI effect.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

2006
Transaction Level Error Susceptibility Model for Bus Based SoC Architectures.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

2005
Transaction-level modeling for architectural and power analysis of PowerPC and CoreConnect-based systems.
Des. Autom. Embed. Syst., 2005

A power estimation methodology for systemC transaction level models.
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005


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