Peide D. Ye

Affiliations:
  • Purdue University, West Lafayette, USA


According to our database1, Peide D. Ye authored at least 17 papers between 2015 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Awards

IEEE Fellow

IEEE Fellow 2013, "For contributions to compound semiconductor MOSFET materials and devices".

Timeline

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Links

On csauthors.net:

Bibliography

2023
Ultrathin Atomic-Layer-Deposited In2O3 Radio-Frequency Transistors with Record High fT of 36 GHz and BEOL Compatibility.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

First Demonstration of BEOL-Compatible Atomic-Layer-Deposited InGaZnO TFTs with 1.5 nm Channel Thickness and 60 nm Channel Length Achieving ON/OFF Ratio Exceeding 10<sup>11</sup>, SS of 68 mV/dec, Normal-off Operation and High Positive Gate Bias Stability.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

Ultrahigh Bias Stability of ALD In2O3 FETs Enabled by High Temperature O2 Annealing.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

FeFET-Based Synaptic Cross-Bar Arrays for Deep Neural Networks: Impact of Ferroelectric Thickness on Device-Circuit Non-Idealities and System Accuracy.
Proceedings of the Device Research Conference, 2023

2022
Determination of Domain Wall Velocity and Nucleation Time by Switching Dynamics Studies of Ferroelectric Hafnium Zirconium Oxide.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Ultra-Fast Operation of BEOL-Compatible Atomic-Layer-Deposited In2O3 Fe-FETs: Achieving Memory Performance Enhancement with Memory Window of 2.5 V and High Endurance > 10<sup>9</sup> Cycles without VT Drift Penalty.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Thermal Studies of BEOL-compatible Top-Gated Atomically Thin ALD In2O3 FETs.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Record RF Performance of Ultra-thin Indium Oxide Transistors with Buried-gate Structure.
Proceedings of the Device Research Conference, 2022

2019
Modeling of Leakage-Assist-Switching in Ferroelectric/Dielectric Stack.
Proceedings of the Device Research Conference, 2019

2018
Low frequency noise in MOS2 negative capacitance field-effect transistor.
Proceedings of the IEEE International Reliability Physics Symposium, 2018

Steep-Slope Hysteresis-Free Negative-Capacitance 2D Transistors.
Proceedings of the 76th Device Research Conference, 2018

High-Performance Few-Layer Tellurium CMOS Devices Enabled by Atomic Layer Deposited Dielectric Doping Technique.
Proceedings of the 76th Device Research Conference, 2018

The Impact of Substrates on the Performance of Top-Gate p-Ga203 Field-Effect Transistors: Record High Drain Current of 980 mA/mm on Diamond.
Proceedings of the 76th Device Research Conference, 2018

2D Ferroelectric CuInP<sub>2</sub>S<sub>6</sub>: Synthesis, ReRAM, and FeRAM.
Proceedings of the 76th Device Research Conference, 2018

Alleviation of Short Channel Effects in Ge Negative Capacitance pFinFETs.
Proceedings of the 76th Device Research Conference, 2018

Time Response of Polarization Switching in Ge Hafnium Zirconium Oxide Nanowire Ferroelectric Field-effect Transistors.
Proceedings of the 76th Device Research Conference, 2018

2015
Characterization and reliability of III-V gate-all-around MOSFETs.
Proceedings of the IEEE International Reliability Physics Symposium, 2015


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