Sheng-Tsung Lai

According to our database, Sheng-Tsung Lai authored at least 5 papers between 2018 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

8.2 A 32Gb/s 12.35Tb/s/mm² 0.36pJ/b UCIe-Like Die-to-Die Interface Featuring Edge-Triggered Transceivers in 3nm with Active LSI Packaging.

Wei-Chih Chen, Mu-Shan Lin, Chien-Chun Tsai, Shenggao Li, Wei-Shuo Lin, Yu-Jie Huang, Nai-Chen Cheng, Yu-Chi Chen, Wen-Hung Huang, Chin-Hua Wen, Hsin-Hung Kuo, Han-Tzung Ke, Jie-Ren Huang, Chang-Yi Li, Sheng-Tsung Lai, Shu-Chun Yang, Kuan-Ting Chou, Pei-Chen Chiou, Tsung-Hsien Tsai, Yi-Ting Chen, Yen-Ming Chen, Kenny Cheng-Hsiang Hsieh

Proceedings of the IEEE International Solid-State Circuits Conference, 2026

2021

A 112-Gb/s PAM-4 Voltage-Mode Transmitter With Four-Tap Two-Step FFE and Automatic Phase Alignment Techniques in 40-nm CMOS.

Pen-Jui Peng, Yan-Ting Chen, Sheng-Tsung Lai, Hsiang-En Huang

IEEE J. Solid State Circuits, 2021

2020

6.8 A 100Gb/s NRZ Transmitter with 8-Tap FFE Using a 7b DAC in 40nm CMOS.

Pen-Jui Peng, Sheng-Tsung Lai, Wei-Hung Wang, Chiang-Wei Lin, Wei-Chien Huang, Ted Shih

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019

A 112Gb/s PAM-4 Voltage-Mode Transmitter with 4-Tap Two-Step FFE and Automatic Phase Alignment Techniques in 40nm CMOS.

Pen-Jui Peng, Yan-Ting Chen, Sheng-Tsung Lai, Chao-Hsuan Chen, Hsiang-En Huang, Ted Shih

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2018

A 50-Gb/s Quarter-Rate Voltage-Mode Transmitter with Three-Tap FFE in 40-nm CMOS.

Pen-Jui Peng, Yan-Ting Chen, Chao-Hsuan Chen, Sheng-Tsung Lai, Hsiang-En Huang, Ho-Hsuan Lu, Tsai-Chin Yu

Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018