Pascal Sainrat

According to our database1, Pascal Sainrat authored at least 47 papers between 1989 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2016
Parallelizing Industrial Hard Real-Time Applications for the parMERASA Multicore.
ACM Trans. Embedded Comput. Syst., 2016

Mapping hard real-time applications on many-core processors.
Proceedings of the 24th International Conference on Real-Time Networks and Systems, 2016

Temporal Isolation of Hard Real-Time Applications on Many-Core Processors.
Proceedings of the 2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), 2016

2014
Minimizing the cost of synchronisations in the WCET of real-time parallel programs.
Proceedings of the 17th International Workshop on Software and Compilers for Embedded Systems, 2014

Time-Predictable Architectures.
FOCUS - Computer Engineering Series, iSTE / Wiley, ISBN: 978-1-84821-593-1, 2014

2013
Automatic WCET Analysis of Real-Time Parallel Applications.
Proceedings of the 13th International Workshop on Worst-Case Execution Time Analysis, 2013

Multi-architecture Value Analysis for Machine Code.
Proceedings of the 13th International Workshop on Worst-Case Execution Time Analysis, 2013


Predictable Two-Level Bus Arbitration for Heterogeneous Task Sets.
Proceedings of the Architecture of Computing Systems - ARCS 2013, 2013

2012
Time analysable synchronisation techniques for parallelised hard real-time applications.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
Éditorial.
Technique et Science Informatiques, 2011

RTOS support for execution of parallelized hard real-time tasks on the MERASA multi-core processor.
Comput. Syst. Sci. Eng., 2011

Predictable bus arbitration schemes for heterogeneous time-critical workloads running on multicore processors.
Proceedings of the IEEE 16th Conference on Emerging Technologies & Factory Automation, 2011

2010
Architecture d'un processeur multiflot orienté temps-réel.
Technique et Science Informatiques, 2010

Merasa: Multicore Execution of Hard Real-Time Applications Supporting Analyzability.
IEEE Micro, 2010

WCET Analysis of a Parallel 3D Multigrid Solver Executed on the MERASA Multi-Core.
Proceedings of the 10th International Workshop on Worst-Case Execution Time Analysis, 2010

OTAWA: An Open Toolbox for Adaptive WCET Analysis.
Proceedings of the Software Technologies for Embedded and Ubiquitous Systems, 2010

RTOS Support for Parallel Execution of Hard Real-Time Applications on the MERASA Multi-core Processor.
Proceedings of the 13th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, 2010

Experimentation of WCET computation on both ends of automotive processor range.
Proceedings of the 1st Workshop on Critical Automotive Applications: Robustness & Safety, 2010

2009
A Context-Parameterized Model for Static Analysis of Execution Times.
Trans. HiPEAC, 2009

2008
WCET 2008 - Report from the Tool Challenge 2008 -- 8th Intl. Workshop on Worst-Case Execution Time (WCET) Analysis.
Proceedings of the 8th Intl. Workshop on Worst-Case Execution Time (WCET) Analysis, 2008

Inter-task WCET computation for a-way instruction caches.
Proceedings of the IEEE Third International Symposium on Industrial Embedded Systems, 2008

An architecture for the simultaneous execution of hard real-time threads.
Proceedings of the 2008 International Conference on Embedded Computer Systems: Architectures, 2008

An improved approach for set-associative instruction cache partial analysis.
Proceedings of the 2008 ACM Symposium on Applied Computing (SAC), 2008

Static Loop Bound Analysis of C Programs Based on Flow Analysis and Abstract Interpretation.
Proceedings of the Fourteenth IEEE Internationl Conference on Embedded and Real-Time Computing Systems and Applications, 2008

A Predictable Simultaneous Multithreading Scheme for Hard Real-Time.
Proceedings of the Architecture of Computing Systems, 2008

2007
High-Performance Embedded Architecture and Compilation Roadmap.
Trans. HiPEAC, 2007

Improving the Worst-Case Execution Time Accuracy by Inter-Task Instruction Cache Analysis.
Proceedings of the IEEE Second International Symposium on Industrial Embedded Systems, 2007

2006
PapaBench: a Free Real-Time Benchmark.
Proceedings of the 6th Intl. Workshop on Worst-Case Execution Time (WCET) Analysis, 2006

Combining Symbolic Execution and Path Enumeration in Worst-Case Execution Time Analysis.
Proceedings of the 6th Intl. Workshop on Worst-Case Execution Time (WCET) Analysis, 2006

Modeling Instruction-Level Parallelism for WCET Evaluation.
Proceedings of the 12th IEEE Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2006), 2006

2005
Régulation du flot d'instructions pour des processeurs orientés temps réel.
Technique et Science Informatiques, 2005

A Case for Static Branch Prediction in Real-Time Systems.
Proceedings of the 11th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2005), 2005

A time-predictable execution mode for superscalar pipelines with instruction prescheduling.
Proceedings of the Second Conference on Computing Frontiers, 2005

2003
Optimisations du chargement des instructions.
Technique et Science Informatiques, 2003

Calcul de majorants de pire temps d'exécution : état de l'art.
Technique et Science Informatiques, 2003

Towards Designing WCET-Predictable Processors.
Proceedings of the 3rd International Workshop on Worst-Case Execution Time Analysis, 2003

2002
Une approche pour réduire la complexité du flot de contrôle dans les programmes C.
Technique et Science Informatiques, 2002

1999
Using the abstract interpretation technique for static pointer analysis.
SIGARCH Computer Architecture News, 1999

Instruction-Level Parallelism and Uniprocessor Architecture - Introduction.
Proceedings of the Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31, 1999

1996
Multiple-Block Ahead Branch Predictors.
Proceedings of the ASPLOS-VII Proceedings, 1996

1995
An investigation of the performance of various instruction-issue buffer topologies.
Proceedings of the 28th Annual International Symposium on Microarchitecture, Ann Arbor, Michigan, USA, November 29, 1995

Exploring Configurations of Functional Units in an Out-of-Order Superscalar Processor.
Proceedings of the 22nd Annual International Symposium on Computer Architecture, 1995

1993
Performance of M3S for the SOR algorithm.
Proceedings of the PARLE '93, 1993

1992
The Design of the M3S: A Multiported Shared-Memory Multiprocessor.
Proceedings of the Proceedings Supercomputing '92, 1992

Towards a Shared-Memory Massively Parallel Multiprocessor.
Proceedings of the 19th Annual International Symposium on Computer Architecture. Gold Coast, 1992

1989
Serial Multiport Memory Multiprocessors.
Proceedings of the PARLE '89: Parallel Architectures and Languages Europe, 1989


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