Andrea Mondelli

Orcid: 0000-0002-4740-7081

Affiliations:
  • Huawei Technologies Co., Ltd.
  • IRISA/INRIA, Rennes, France (former)


According to our database1, Andrea Mondelli authored at least 11 papers between 2015 and 2023.

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Bibliography

2023
IXIAM: ISA EXtension for Integrated Accelerator Management.
IEEE Access, 2023

Analysis and Optimization of Direct Convolution Execution on Multi-Core Processors.
IEEE Access, 2023

Energy and Performance Improvements for Convolutional Accelerators Using Lightweight Address Translation Support.
Proceedings of the 20th ACM International Conference on Computing Frontiers, 2023

2022
A survey on hardware accelerators: Taxonomy, trends, challenges, and perspectives.
J. Syst. Archit., 2022

A General Framework for Accelerator Management Based on ISA Extension.
IEEE Access, 2022

2021
SeMPE: Secure Multi Path Execution Architecture for Removing Conditional Branch Side Channels.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020
The gem5 Simulator: Version 20.0+.
CoRR, 2020

2017
Revisiting Wide Superscalar Microarchitecture.
PhD thesis, 2017

2015
Revisiting Clustered Microarchitecture for Future Superscalar Cores: A Case for Wide Issue Clusters.
ACM Trans. Archit. Code Optim., 2015

Dataflow Support in x86_64 Multicore Architectures through Small Hardware Extensions.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

Enhancing an x86_64 multi-core architecture with data-flow execution support.
Proceedings of the 12th ACM International Conference on Computing Frontiers, 2015


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